Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N?1 groups and the plurality of parity bits form a first group different from the N?1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N?1 groups; and providing a second word comprising updated data bits that form a second one of the N?1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N?1 groups.

Abstract: A method for responding to a read request from a user for a set of encoded data slices (EDSs) in a distributed storage network begins with a processing module determining that a threshold number of encoded data slices is not available and continues with the processing module determining that one or more copies are available for the set of EDSs. The method continues with the processing module determining whether a combination of the one or more additional EDSs within the copy of the set of EDSs and the available EDSs from the set of EDSs is at least a read threshold number of EDSs, and when a read threshold is available based on the combination the processing module responds to the request using the combination.

Abstract: A memory system comprises a memory device including a plurality of memory blocks, the memory device being configured to perform a program operation and a program verify operation to program data to the memory blocks, and a controller configured to detect program error bit information as a result of the program verify operation, select a victim memory block among the memory blocks based on the detected program error bit information, and copy programmed data of the victim memory block.

Abstract: Invention achieves reduced amount of terminals to control a test mode, test function and test results of a given standard for at least one “wrapped core” (40,100) (a core 100 surrounded by a wrapper boundary register (40) as “wrapper chain”). Test flexibility and speed of testing the core (100) are also improved. Suggested serial test interface comprises a state machine (210) and an instruction register (213) for wrapper-instructions, supplied through a single physical data input terminal (1a). The state machine (210) reads wrapper-instructions held by the instruction register (213) and generates on-chip wrapper control signals (30) of the given standard for the wrapper boundary register (40) of the core (100). At least one wrapper-instruction read from the Instruction Register (213) provides at least one wrapper control signal (30). The single input terminal (1a) also supplies an input test signal SDI for coupling to the wrapper boundary register (40) as on chip logical input test signal WSI.

Abstract: Processing load and incoming inter-zone network traffic for remote zones during geographically distributed (GEO) erasure coding can be reduced. In one aspect, GEO erasure coding can be performed in multiple phases, wherein each phase can be distributed between zones. Moreover, during a first phase, partially-finished coding chunks can be generated by frontend zones. Further, during an intermediate phase, partially-finished coding chunks that are associated with a common coding chunk can be transferred between the frontend zones and combined to generate consolidated partial coding chunks. Furthermore, during a final phase, the remote zones can receive and combine the consolidated partial coding chunks to generate a complete coding chunk that can be utilized for data recovery.

Abstract: An interconnection network for providing data transfer between a plurality of nodes of an integrated circuit comprises a number of endpoints for exchanging data with respective nodes of the integrated circuit, a primary network to route a primary payload from a source endpoint to a destination endpoint; and a redundant network to route, to the destination endpoint, a redundant payload comprising a first check code calculated based on at least a portion of the primary payload, the first check code having fewer bits than said at least a portion of the primary payload. The destination endpoint comprises error checking circuitry to perform an error checking operation to calculate a second check code based on the primary payload received via the primary network, and verify integrity of the primary payload based on a comparison of the second check code with the first check code received via the redundant network.

Abstract: A memory device is configured to provide internal or on-die ECC (error checking and correction or error correction coding). In such a system, the code matrix can be managed as four quadrants of (N/4) bits, with two adjacent quadrants in an (N/2)-bit segment or portion. The N codes of the matrix correspond to the N bits of a data word to be protected by the ECC. The code matrix includes M codes corresponding to the M ECC check bits. The memory device includes internal ECC circuitry to perform ECC in the DRAM device with the ECC bits and code matrix in response to a request to access the data word. The codes in a quadrant steer an aliased bit to a quadrant other than an adjacent quadrant.

Abstract: A first parity calculator calculates one parity bit for serial binary data to be subjected to a conversion process. A second parity calculator calculates one parity bit for serial binary data obtained as a result of the conversion process. When both parity bits do not match, a multiplexer outputs, as a parity bit of the serial binary data obtained as a result of the conversion process, a parity bit obtained by inverting one parity bit included in the serial binary data to be subjected to the conversion process.

Abstract: A transfer device includes: a converter configured to convert an address contained in a command CMD1 transmitted from a master device, to an address indicating an internal slave device, and transfer a command CMD2K to the stated internal slave device; a first parity calculator configured to calculate a first parity bit formed of one bit for the command CMD2K; and a judgment circuit configured to judge whether or not a predetermined abort condition is satisfied. When the predetermined abort condition is satisfied, the converter outputs the first parity bit as a parity bit of the command CMD2K.

Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract: A semiconductor device includes: a fuse set unit including a plurality of fuse sets, each fuse set including one or more address fuses and an enable fuse; a rupture control unit suitable for controlling the enable fuse of a selected fuse set to be programmed after the address fuses of the selected fuse set is programmed, during a program operation; a cell data verify unit suitable for repeatedly performing a verify and rupture operation on the selected fuse set during the program operation, determining whether read data from the selected fuse set is identical to target data corresponding to a rupture address through a final verify operation, and outputting fail information; and a fuse set control unit suitable for controlling the program operation to be performed on a different fuse set after the program operation on the selected fuse set is terminated, in response to the fail information.

Abstract: Some embodiments include apparatuses and methods having an interface to receive information from memory cells, the memory cells configured to have a plurality of states to indicate values of information stored in the memory cells, and a control unit to monitor errors in information retrieved from the memory cells. Based on the errors in the information, the control unit generates control information to cause the memory cell to change to from a state among the plurality of states to an additional state. The additional state is different from the plurality of states.

Abstract: Embodiments include techniques for using circuit structures for resolving random testability, the techniques includes analyzing a logic structures of a circuit design, and identifying the logic structures of the circuit that are random resistant structures. The techniques also include replacing the logic structures with random testable structures, and performing a test of the circuit design.

Abstract: A technique relates to operating a memory controller. The memory controller drives first memory devices and second memory devices of the memory controller in a dual channel mode. A first error correcting code (ECC) memory device and a second ECC memory device protect the first memory devices and the second memory devices. The memory controller drives the first memory devices and the second memory devices in a single channel mode such that the second ECC memory device is a spare memory device, and the first ECC memory device protects the first memory devices and the second memory devices. The memory controller is configured to switch between the dual channel mode and the single channel mode.

Abstract: Embodiments include techniques for using circuit structures for resolving random testability, the techniques includes analyzing a logic structures of a circuit design, and identifying the logic structures of the circuit that are random resistant structures. The techniques also include replacing the logic structures with random testable structures, and performing a test of the circuit design.

Abstract: The disclosed embodiments are directed to systems, devices, and methods for iterative message-passing decoding. In one embodiment, a method is disclosed comprising decoding a first codeword at a storage device using a detector and a decoder, the first codeword comprising a set of symbols from a first set of codewords; assigning, via the decoding, a set of confidence levels for each symbol in the first codeword; transmitting, by the storage device, the confidence levels to an iterative decoder; generating, by the iterative decoder, a second codeword based on the set of confidence levels, the second codeword excluding at least one symbol in the set of symbols; and iteratively decoding, by the iterative decoder, the second codeword using an erasure decoder; and transmitting, by the iterative decoder, soft information generated by the erasure decoder to the storage device for subsequent decoding by the storage device.

Abstract: The disclosure is related to an RF signal processing apparatus. The apparatus includes a processor and a buffer memory circuit. The apparatus includes a host interface for connecting with a host and an RF circuit for transmitting and receiving RF signals. The processor processes the RF signals to or from the RF circuit. The processor converts the received RF signals into data, or converts the data into the RF signals to be transmitted. The buffer memory circuit has a controller and two buffer memories. This memory architecture allows a system to assign a task to a first buffer memory and another task to a second buffer memory without restricting that the conventional buffer memory is limited to doing one task at a time. This memory architecture can solve inefficiency problems due to insufficient data transmission since the conventional buffer memory cannot be filled within a limited time period.

Abstract: A bit tagging method, a memory control circuit unit and a memory storage device are provided. The method includes: reading first memory cells according to a first reading voltage to generate a first codeword and determining whether the first codeword is a valid codeword, and the first codeword includes X bits; if not, reading the first memory cells according to a second reading voltage to generate a second codeword and determining whether the second codeword is the valid codeword, and the second codeword includes X bits; and if the second codeword is not the valid codeword and a Yth bit in the X bits of the first codeword is different from a Yth bit in the X bits of the second codeword, recording the Yth bit in the X bits as an unreliable bit, and Y is a positive integer less than or equal to X.

Abstract: A specific UTC time corresponding to a specific NPT time is appropriately obtained in a reception side without being influenced by occurrence of a leap second. Transmission media of a program are transmitted, and mapping information between an NTP time represented by a relative time from a beginning of a program and a UTC time represented by an absolute time is intermittently transmitted. Leap second adjustment information is included in the mapping information. In the reception side, the specific UTC time corresponding to the specific NPT time obtained on the basis of the mapping information can be adjusted on the basis of the leap second adjustment information, and the influence of occurrence of the leap second can be avoided.