Abstract: A method and a circuit for implementing dynamic single event upset (SEU) detection and correction, and a design structure on which the subject circuit resides are provided. The circuit implements detection, correction and scrubbing of unwanted state changes due to SEUs, noise or other event in semiconductor circuits. The circuit includes a plurality of L1 L2 latches connected in a chain, each L1 L2 latch includes an L1 latch and an L2 latch with the L2 latch having a connected output monitored for a flip. A single L2 detect circuit exclusive OR (XOR) is connected to each L2 latch. An L2 detect circuit XOR tree includes an input connected to a true output of a respective L2 latch in the chain. An L2 clock (LCK) trigger circuit is connected to an output of the L2 detect circuit XOR tree and is shared across each of the plurality of L1 L2 latches for correcting bit flip errors.

Abstract: A transmitting device for generating a digital television broadcast signal incudes circuitry configured to receive data to be transmitted in a digital television broadcast signal and perform LDPC (low density parity check) encoding on input bits of the received data according to a parity check matrix initial value table of an LDPC code having a code length of 16200 bits and a code rate of 10/15 to generate an LDPC code word. The LDPC code enables error correction processing to correct errors generated in a transmission path of the digital television broadcast signal. The LDPC code word includes information bits and parity bits, the parity bits being processed by the receiving device to recover information bits corrupted by transmission path errors.

Abstract: A plurality of failure domains are communicatively coupled to each other via a network, and each of the plurality of failure domains is coupled to one or more storage devices. A failure resilient stripe is distributed across the plurality of storage devices, such that two or more blocks of the failure resilient stripe are located in each failure domain.

Abstract: Apparatuses including a test interface circuit that is configured to merge multiple independent traffic streams generated from individual algorithmic pattern generators (APGs) for communication with a memory device over a shared memory interface. The combination of multiple independent traffic streams, each with their own looping sequences and command timings, may generate a large set of random command sequences. The test interface circuit may include an arbiter circuit that merges a first independent traffic stream from a first APG and a second independent traffic stream from a second APG. Each of the first and second independent traffic streams are directed to different semi-independently-accessible portions of the memory device. The memory device may include a hybrid memory cube having independently accessible vaults or a high bandwidth memory device having independently accessible channels, in some examples.

Abstract: A memory scrubbing system includes a persistent memory device coupled to an operating system (OS) and a Basic Input/Output System (BIOS). During a boot process and prior to loading the OS, the BIOS retrieves a known memory location list that identifies known memory locations of uncorrectable errors in the persistent memory device and performs a partial memory scrubbing operation on the known memory locations. The BIOS adds any known memory locations that maintain an uncorrectable error to a memory scrub error list. The BIOS then initiates a full memory scrubbing operation on the persistent memory device, cause the OS to load and enter a runtime environment while the full memory scrubbing operation is being performed, and provides the memory scrub error list to the OS.

Abstract: In response to determining that an application programming interface call made in response to a first request for the call has failed and that no fail entry has been set for the call, aspects increment a fail count value and set a fail entry for the call that includes a fail response generated by the failure of the call; in response to determining that the call has failed in response to a subsequent, second request for the call, determine whether the incremented fail count value meets a limit value, and if so, set a paused timestamp value for the fail entry; and in response to additional requests for the call occurring within a pause period of time from the paused timestamp value, pause making the call and return the fail entry set for the call in satisfaction of said additional requests.

Abstract: In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface.

Abstract: A method for generating a polar code cN of length N and dimension K, on the basis of a generator matrix GN of size N×N, is provided. The method includes generating a distance spectrum vector dTp=(dTp(1), . . . , dTp(p)) of size p of the kernel Tp, wherein dTp(h), h=1, . . . , p, corresponds to a maximum value among all possible minimum distances of all possible polar codes of size p and dimension h generated on the basis of the kernel Tp. The method also includes generating a distance spectrum vector dGN of size N of the generator matrix GN on the basis of the distance spectrum vector dTp, determining the set of K information bit indices I on the basis of the distance spectrum vector dGN, and generating the polar code cN on the basis of the set of K information bit indices I.

Abstract: A memory system includes a Nonvolatile Memory (NVM) and storage circuitry. The NVM includes memory cells organized in multiple memory blocks that each includes multiple Word Lines (WLs). The storage circuitry assigns in a recovery scheme, data pages to predefined parity groups, including assigning to a parity group multiple data pages of two or more different bit-significance values in a common group of the memory cells in a WL. The storage circuitry calculates redundancy data over the data pages of a given parity group in accordance with the recovery scheme and stores the redundancy data in a dedicated group of the memory cells. The storage circuitry reads a data page belonging to the given parity group, and upon detecting a read failure, recovers the data page based on other data pages in the given parity group and on the redundancy data calculated for the given parity group.

Abstract: A storage client needs to store to-be-written data into a distributed storage system, and storage nodes corresponding to a first data unit assigned for the to-be-written data by a management server are only some nodes in a storage node group. When receiving a status of the first data unit returned by the management server, the storage client may determine quantities of data blocks and parity blocks needing to be generated during EC coding on the to-be-written data. The storage client stores the generated data blocks and parity blocks into some storage nodes designated by the management server in a partition where the first data unit is located. Accordingly, dynamic adjustment of an EC redundancy ratio is implemented, and the management server may exclude some nodes in the partition from a storage range of the to-be-written data based on a requirement, thereby reducing a data storage IO amount.

Abstract: A controller for controlling a memory device includes a read control component suitable for controlling a recovery soft read operation of the memory device on bits contained in error correction-failed data groups, when error correction on data of a target data group and error correction on one or more of data of corresponding data groups failed; an error correction code (ECC) component suitable for performing the error correction, and performing a selective data recovery operation on the target data group depending on reliabilities of the respective bits, derived as a result of the recovery soft read operation; and a read bias determiner suitable for determining a recovery soft read voltage to maximize the number of bits recovered by the selective data recovery operation, among bits contained in the target data group.

Abstract: The present disclosure provides a method, system, and terminal device for data transmission in an unlicensed spectrum, effectively reduce mutual signal interference between different systems while meeting regulation constraints on use of the unlicensed spectrum. The method in the present disclosure includes: at a processing start moment of a terminal device in a current channel occupancy time window of a network device, when remaining duration of the current channel occupancy time window of the network device is greater than or equal to duration for the terminal device to transmit a to-be-sent data packet to the network device, selecting based on a user attribute of the terminal device and from a mapping relationship between a user attribute and a transmission mode; and sending the to-be-sent data packet to the network device in the selected transmission mode.

Abstract: A method includes calculating a first position encoded pattern based on a first data pattern, and using an automata processor to compare the first position encoded pattern to a second position encoded pattern to identify a second data pattern within the first data pattern.

Abstract: Systems, apparatuses, and methods for implementing debug features on a secure coprocessor to handle communication and computation between a debug tool and a debug target are disclosed. A debug tool generates a graphical user interface (GUI) to display debug information to a user for help in debugging a debug target such as a system on chip (SoC). A secure coprocessor is embedded on the debug target, and the secure coprocessor receives debug requests generated by the debug tool. The secure coprocessor performs various computation tasks and/or other operations to prevent multiple round-trip messages being sent back and forth between the debug tool and the debug target. The secure coprocessor is able to access system memory and determine a status of a processor being tested even when the processor becomes unresponsive.

Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of memory cells of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of memory cells of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of memory cells of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block of memory cells.

Abstract: Disclosed are a nonvolatile memory and an operation method thereof. The nonvolatile memory includes a memory cell array and a controller. The controller is configured to: read out raw data from a plurality of memory cells in the memory cell array; correct the raw data by using error correction code (ECC) data to obtain corrected data; determine an address of a memory cell having a data loss error in the plurality of memory cells; and program the memory cell having the data loss error. After the ECC correction in the read operation, the data loss error is corrected by a program operation.

Abstract: A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and determines a first directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times.

Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure different blocks of the plurality of blocks of memory cells in different configurations, which can include blocks configured to include only groups of user data memory cells for storing user data, blocks configured to include only groups of overhead data memory cells for storing error correction code (ECC) data, and blocks configured to include groups of user data memory cells and groups of overhead data memory cells.

Abstract: A low-density parity-check code scaling method is disclosed. The method includes following steps: obtaining the original low-density parity-check matrix; forming the permutation matrices with the random row shift or the random column shift to the identity matrix; replacing the component codes by the permutation matrices and the all-zero matrix to form the extended low-density parity-check matrix; adjusting the code length and the code rate to form the global coupled low-density parity-check matrix; and outputting the global coupled low-density parity-check code.

Abstract: A highly programmable device, referred to generally as a data processing unit, having multiple processing units for processing streams of information, such as network packets or storage packets, is described. The data processing unit includes one or more specialized hardware accelerators configured to perform acceleration for various data-processing functions. This disclosure describes a parallel decoding of codewords within input data stream based on a codeword type and position.