Abstract: One embodiment facilitates global data placement in a storage device. The system receives a request to write first data. The system selects one of a plurality of physical media of the storage device to which to directly write the first data, based on a frequency of access, a block size, and a latency requirement of the first data, wherein the plurality of physical media includes a fast cache medium, a solid state drive, and a hard disk drive. In response to determining that the frequency of access of the first data is greater than a predetermined threshold, or in response to determining that the block size associated with the first data is not greater than a predetermined size and determining that the first data is an update to existing data, the system selects the fast cache medium. The system writes the first data to the selected one physical medium.

Abstract: A variety of applications can include apparatus and/or methods that provide parity protection to data spread over multiple memory devices of a memory system. Parity is stored in a buffer, where the parity is generated from portions of data written to a page having a different portion of the page in a portion of each plane of one or more planes of the multiple memory devices. Parity is stored in the buffer for each page. In response to a determination that a transfer criterion is satisfied, the parity data in the buffer is transferred from the buffer to a temporary block. After programming data into the block to close the block, a verification of the block with respect to data errors is conducted. In response to passing the verification, the temporary block can be released for use in a next data write operation. Additional apparatus, systems, and methods are disclosed.

Abstract: A data coding device includes an error correction coder that converts user data into ECC data by error correction coding, a modulation coder that converts the ECC data into a series of modulated code data, a detector that detects a local concentration of modulation marks/modulation spaces that are shorter than or equal to a prescribed minimum run-length plus N from the series of modulated code data, a conversion determiner that judges whether to convert the series of modulated code data into another series of modulated code data, according to a concentration, detected by the detector, of the modulation marks/modulation spaces, and a modulation data converter that converts the series of modulated code data into the another series of modulated code data.

Abstract: One embodiment provides a system and method for storing data. During operation, the system receives a to-be-written data chunk, sends the to-be-written data chunk to a first and second storage devices. The system performs first and second error-correction-code (ECC) encoding operations on the to-be-written data chunk prior to writing the to-be-written data chunk to the first and second storage media associated with the first and second storage devices, respectively. The first storage medium has a first access granularity and a first raw-error-rate (RER). The second storage medium has a second access granularity and a second RER. The first access granularity is smaller than the second access granularity, the first RER is greater than the second RER, and the second ECC encoding operation has a stronger error-correction capability than the first ECC encoding operation.

Abstract: A transmitter may select a control message format of a set of possible control message formats, each of the possible control message formats corresponding to a different number of information bits. The transmitter may polar encode a payload in the selected control message format to generate and transmit a polar-encoded codeword, the payload having a same number of bits for any of the set of possible control message formats. A receiver may determine the set of possible control message formats for the polar-encoded codeword, and may decode the polar-encoded codeword to identify a candidate control message. The receiver may identify a control message format in the set of possible control message formats for the candidate control message based on multiple hypotheses corresponding to the different number of information bits, and may obtain control information from the candidate control message based on the identified control message format.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller calculates a reliability metric on the basis of at least a soft-decision input value calculated on the basis of read information that is read from the nonvolatile memory, and a decoded word, stores reference information that is a history of a plurality of reliability metrics or statistical information obtained from the history, calculates reliability from the reliability metric by using correspondence information, calculates decoding information on the basis of the decoded word and the reliability, and updates the correspondence information on the basis of the reference information.

Abstract: In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.

Abstract: Methods and apparatus for increasing spectral efficiency in non-orthogonal multiple access (NOMA) communication, that implement receiving a signal stream from a user, splitting the signal stream into a plurality of sub-streams, applying a forward error coding (FEC) to each one of the sub-streams, and outputting a corresponding plurality of FEC encoded sub-streams. This can include modulating a corresponding carrier with each of the FEC encoded sub-streams, and combining and transmitting the corresponding plurality of modulated carrier signals. The modulated carrier signals can each carry a respective one of the FEC encoded sub-streams.

Abstract: An apparatus includes a first circuit and a second circuit. The first circuit may be configured to generate a launch signal synchronized with a first clock signal in a first clock domain. The second circuit may be configured to (i) receive a second clock signal in a second clock domain and (ii) generate a plurality of pulses in each of a third clock signal and a fourth clock signal based on the second clock signal and the launch signal. A frequency of the pulses in the fourth clock signal may be an integer multiple of another frequency of the pulses in the third clock signal. An initial one of each of the pulses in the third clock signal and the fourth clock signal may be synchronized with each other.

Abstract: A communication method and system for converging a 5th-generation (5G) communication system for supporting higher data rates beyond a 4th-generation (4G) system with a technology for internet of things (IoT) are provided. The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The method and apparatus for polar encoding and rate-matching are disclosed.

Abstract: A method and circuit are disclosed to calculate an error correction code (ECC) and perform a decryption in parallel when reading memory data. There are multiple modes of operation. In a normal parallel mode of operation, the data passes through a decryption engine. Simultaneously, the same data passes through an ECC decode engine. However, if no error is detected, the output of the decode engine is discarded. If there is an ECC error, an error indication is made so that the corresponding data exiting the decryption engine is discarded. The circuit then switches to a serial mode of operation, wherein the ECC decode engine corrects the data and resends the corrected data again through the decryption engine. The circuit is maintained in the serial mode until a decision is made to switch back to the parallel mode, such as when a pipeline of the ECC engine becomes empty.

Abstract: Devices and methods may be used to append a scalable (1) of parity bits in a data packet that scales with a number of data bits in a payload of the data packet. The parity bits may be generated utilizing a table of entries. In some examples, each entry in the table corresponds to a number of the data bits to be included in the payload; and each column of the table may be used to generate a corresponding parity bit of the one or more parity bits.

Abstract: A method for operating a memory system includes: performing a read operation in response to a first tag; performing a read operation in response to a second tag; performing a defense code operation corresponding to the first tag; performing an error correction code (ECC) operation on data output through the defense code operation corresponding to the first tag; and performing a defense code operation corresponding to the second tag, wherein the read operation in response to the second tag is started before the ECC operation corresponding to the first tag is completed, and wherein the defense code operation corresponding to the second tag is performed using a result of the defense code operation corresponding to the first tag.

Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.

Abstract: Systems and methods disclosed herein provide for improved testing of memory error correction code (“ECC”) logic with memory built-in self-test (“MBIST”). Embodiments provide for a masking element to inject one or more faults into the ECC logic during at least one of a manufacturing test (“MFGT”) and a power-on-self-test (“POST”), wherein, based on the injected faults, it can be determined if the ECC logic contains any errors.

Abstract: Embodiment techniques map parity bits to sub-channels based on their row weights. In one example, an embodiment technique includes polar encoding, with an encoder of the device, information bits and at least one parity bit using the polar code to obtain encoded data, and transmitting the encoded data to another device. The polar code comprises a plurality of sub-channels. The at least one parity bit being placed in at least one of the plurality of sub-channels. The at least one sub-channel is selected from the plurality of sub-channels based on a weight parameter.

Abstract: Provided herein may be a circuit for transforming a parity-check matrix of a Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) code, an error correction circuit having the same, and a method of operating the same. The circuit for transforming a parity check matrix of a QC-LDPC code including circulant matrices may include a determination component configured to determine whether a parity-check matrix that is externally input has full rank, a selection component configured to detect linearly dependent rows or columns, among rows or columns of the parity-check matrix based on a result of the determination of the determination component, and select any one row or column from among the linearly dependent rows or columns, and an entry replacement component configured to replace any one of circulant matrices included in the selected one row or column with a zero matrix.

Abstract: A device, system and method are provided for wirelessly transmitting a sequence of video packets containing video data for one or more video frames. An importance metric associated with a priority of transmitting each individual packet in the sequence of video packets is independently computed, a retry limit or packet lifetime for each individual video packet in the sequence of video packets is independently determined based on the importance metric, and each video packet in the sequence of video packets is attempted to be transmitted. If the transmission attempt for an individual video packet in the sequence fails, the transmission attempt is repeated for up to the retry limit or the packet lifetime independently determined for the individual packet or until a successful transmission is achieved, whichever occurs first.

Abstract: An encoding method and encoder of a time-varying LDPC-CC with high error correction performance are provided. In an encoding method of performing low density parity check convolutional coding (LDPC-CC) of a time varying period of q using a parity check polynomial of a coding rate of (n?1)/n (where n is an integer equal to or greater than 2), the time varying period of q is a prime number greater than 3, the method receiving an information sequence as input and encoding the information sequence using Equation 1 as a g-th (g=0, 1, . . . , q?1) parity check polynomial to satisfy 0.

Abstract: The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 16200 bits and an encoding rate r is 6/15, 8/15, or 10/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code.