Patents Examined by Guillermo Egoavil
  • Patent number: 9549469
    Abstract: A printed circuit board assembly and method of assembly is provided for a printed circuit board having a top and bottom surface with at least one edge portion having a rounded surface extending from the top surface to a point below the top surface and at least one electrical contact pad located on the top surface and extending over the edge portion rounded surface to a point below the top surface.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: January 17, 2017
    Assignee: International Business Machines Corporation
    Inventor: Brian Samuel Beaman
  • Patent number: 9543266
    Abstract: Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center and parallel to the wire longitudinal direction (wire center cross-section), there are no crystal grains with a ratio a/b of a long axis “a” and a short axis “b” of 10 or more and with an area of 15 ?m2 or more (“fiber texture”), (2) when measuring a crystal direction in the wire longitudinal direction in the wire center cross-section, the ratio of crystal direction <100> with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 10% to less than 50%, and (3) when measuring a crystal direction in the wire longitudinal direction at the wire surface, the ratio of crystal direction <100> with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 70% or more. During the drawing step, a drawing operation with a rate of reduction of area of 15.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: January 10, 2017
    Assignees: NIPPON MICROMETAL CORPORATION, NIPPON STEEL & SUMIKIN MATERIALS CO., LTD
    Inventors: Takashi Yamada, Daizo Oda, Ryo Oishi, Teruo Haibara, Tomohiro Uno
  • Patent number: 9536854
    Abstract: Bonding wire for semiconductor device use where both leaning failures and spring failures are suppressed by (1) in a cross-section containing the wire center and parallel to the wire longitudinal direction (wire center cross-section), there are no crystal grains with a ratio a/b of a long axis “a” and a short axis “b” of 10 or more and with an area of 15 ?m2 or more (“fiber texture”), (2) when measuring a crystal direction in the wire longitudinal direction in the wire center cross-section, the ratio of crystal direction <100> with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 50% to 90%, and (3) when measuring a crystal direction in the wire longitudinal direction at the wire surface, the ratio of crystal direction <100> with an angle difference with respect to the wire longitudinal direction of 15° or less is, by area ratio, 50% to 90%. During the drawing step, a drawing operation with a rate of reduction of area of 15.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: January 3, 2017
    Assignees: NIPPON MICROMETAL CORPORATION, NIPPON STEEL & SUMIKIN MATERIALS CO., LTD
    Inventors: Takashi Yamada, Daizo Oda, Ryo Oishi, Teruo Haibara, Tomohiro Uno
  • Patent number: 9530537
    Abstract: The present disclosure is directed to a halogen-free composition and conductors coated with the halogen-free composition. The halogen-free composition includes (A) from 70 wt % to 85 wt % of a polymeric component and (B) from 30 wt % to 15 wt % of a halogen-free flame retardant. The polymeric component (A) includes (i) a propylene homopolymer or a mini-random copolymer with greater than 40% crystallinity and (ii) an ethylene/a-olefin copolymer. The halogen-free composition has a density less than 1.15 g/cc. The halogen-free composition also has a scrape abrasion resistance of greater than or equal to 350 cycles as measured in accordance with ISO 6722.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: December 27, 2016
    Assignee: Dow Global Technologies LLC
    Inventors: Caroline H. Laufer, Lin Fu, Thomas S. Lin, Matthew T. Bishop, Hamed Lakrout
  • Patent number: 9514884
    Abstract: A multilayer ceramic electronic component is provided including a ceramic body having dielectric layers and a plurality of internal electrodes disposed in the ceramic body. The internal electrodes have exposed portions exposed to the exterior of the ceramic body. An electrode layer is disposed on an outer surface of the ceramic body electrically connected to the exposed portions of the internal electrodes A conductive resin layer is disposed on the electrode layer. The electrode layer has an uneven surface.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: December 6, 2016
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Kyoung No Lee, Byung Jun Jeon, Eun Me Park, Chang Hoon Kim, Byong Gyun Kim
  • Patent number: 9514859
    Abstract: Heat resistant cables and cords that are used with portable communications equipment wherein the user thereof must be able to operate in extremely hostile environments including being present in a fire are requisite in order to provide continual communications. These fire and heat resistant cables and cords ensure that emergency responders, such as fire and rescue responders, using such a communications system is in constant contact with others on the team and also with the outside so as to be able to call in for help or additional resources and thus ensure the safety of that first responder.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: December 6, 2016
    Assignee: WHITNEY BLAKE COMPANY
    Inventor: Timothy Allen Scarpa
  • Patent number: 9507390
    Abstract: Provided is a magnetic field shield sheet for a digitizer, which blocks an effect of a magnetic field generated from various components of a main body of the portable terminal device and at the same time improves the sensitivity of an electronic pen when a digitizer feature is implemented in the portable terminal device, while minimizing an influence upon a geomagnetic sensor. The magnetic field shield sheet includes: at least one layer thin magnetic sheet made of a nanocrystalline alloy and flake-treated so as to be separated into a plurality of fine pieces; a protective film that is adhered on one surface of the thin magnetic sheet via a first adhesive layer provided on one side of the protective film; and a double-sided tape that is adhered on the other surface of the thin magnetic sheet via a second adhesive layer provided on one side of the double-sided adhesive tape.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: November 29, 2016
    Assignee: AMOSENSE CO., LTD.
    Inventors: Kil Jae Jang, Dong Hoon Lee, Dong Kun Lee
  • Patent number: 9510449
    Abstract: Embodiments of the present disclosure relate to the field of electronics and, in particular, to a multi-layer printed circuit board and a method for fabricating the same. The circuit board is able to avoid the problem that signal transmission performance is affected by a plated hole. The multi-layer printed circuit board includes at least two layers of core plates that are adhered, where a circuit mechanical part is disposed on the core plates, a via is also provided on the core plates, and a metal column is embedded in the via, where one end of the metal column is connected to a corresponding position on an antenna feeder circuit mechanical part disposed on the core plate, and the other end is connected to a corresponding position on an antenna feeder circuit mechanical part disposed on an adjacent layer of the core plate. The method is used for fabricating a multi-layer printed circuit board.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: November 29, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mingli Huang, Tao Feng, Songlin Li
  • Patent number: 9496071
    Abstract: In a shield wire, a sheet shaped metal foil shield member is provided so as to envelop an inner wire part having a plurality of conductors and insulators. In the shield wire, the inner wire part is enveloped by the metal foil shield member so that the inner wire part is held and an end part of the metal foil shield member is avoided from collapsing or the end is avoided from bounding.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: November 15, 2016
    Assignee: YAZAKI CORPORATION
    Inventor: Mitsuharu Nagahashi
  • Patent number: 9490050
    Abstract: An electric conductor may be provided. The electric conductor may comprise a conductor core and a plurality of conductor strands wrapped around the conductor core. The conductor core may comprise a plurality of core strands comprising an overall number of strands. The plurality of core strands may comprise a first portion of core strands and a second portion of core strands. The first portion of core strands may comprise a first number of strands. The first portion of core strands may comprise steel. The second portion of core strands may comprise a second number of strands. The second portion of core strands may comprise a composite material. A ratio of the first number of strands to the overall number of strands and a ratio of the second number of strands to the overall number of strands may be optimized to give the conductor core a predetermined characteristic.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: November 8, 2016
    Assignee: Southwire Company, LLC
    Inventor: Mark A. Lancaster
  • Patent number: 9491871
    Abstract: A carrier substrate includes a dielectric layer, a first circuit layer, an insulation layer, conductive blocks, and a first conductive structure. The dielectric layer has a first surface, a second surface, and blind vias. The first circuit layer is embedded in the first surface and the blind vias extend from the second surface to the first circuit layer. The insulation layer is disposed on the first surface and has a third surface, a fourth surface, and first openings exposing the first circuit layer. The conductive blocks fill the first openings and connect with the first circuit layer. A top surface of each of the conductive blocks is higher than the third surface of the insulation layer. The first conductive structure includes conductive vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: November 8, 2016
    Assignee: Unimicron Technology Corp.
    Inventors: Ying-Chih Chan, Chun-Ting Lin
  • Patent number: 9462684
    Abstract: A wiring material includes conductors, each of which has a cross section having a thickness and a width not less than the thickness, a trunk portion in which the conductors are spaced parallel in a direction of the width thereof, a branch portion in which each conductor is bent and branched from the trunk portion in the direction of the width or in a direction that intersects the direction of the width, and a covering member for covering the trunk portion and the branch portion to expose both ends of the conductors.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: October 4, 2016
    Assignee: Hitachi Metals, Ltd.
    Inventors: Kotaro Tanaka, Toshiyuki Horikoshi, Takumi Sato, Kenichi Murakami
  • Patent number: 9451711
    Abstract: A printed wiring board includes an insulating substrate having a penetrating hole formed through the substrate, a first conductive pattern formed on first surface of the substrate, a second conductive pattern formed on second surface of the substrate on the opposite side of the first surface, and a through-hole conductor formed in the penetrating hole in the substrate such that the conductor is connecting the first conductive pattern on the first surface of the substrate and the second conductive pattern on the second surface of the substrate. The penetrating hole has a first opening portion opening on the first surface of the substrate, a second opening portion opening on the second surface of the substrate and a third opening portion connecting the first and second opening portions, and the third opening portion has the maximum diameter which is greater than the minimum diameters of the first and second opening portions.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: September 20, 2016
    Assignee: IBIDEN CO., LTD.
    Inventor: Toshiaki Hibino
  • Patent number: 9443788
    Abstract: A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: September 13, 2016
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventor: Takamasa Takano
  • Patent number: 9439285
    Abstract: In the upper surface of a metallic substrate, a region near the central part of the metallic substrate is surrounded by a rectangle having dotted sides electrically separate the interior and exterior of the rectangle. Each dot of the sides is formed of a pillared insulating resin that penetrates from the upper surface to the lower surface of the metallic substrate. Oxide films are so formed as to fill in the spaces between adjacent cylinders of insulating resins and the surrounding of the cylinders. That is, a separation layer is formed of the pillared insulating resins and the oxide films that fill up the spaces between the pillared insulating resins as well as their vicinities.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: September 6, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Keishi Kato, Osamu Tabata, Yoshio Okayama, Ryosuke Usui
  • Patent number: 9439301
    Abstract: There is provided a multilayered chip electronic component including: a ceramic body including internal electrodes and dielectric layers; external electrodes covering both end surfaces of the ceramic body in a length direction; first plating layers forming the external electrodes and formed on outer surfaces of the ceramic body; non-conductive layers formed on outer side surfaces of the first plating layers; and second plating layers formed on regions of the first plating layers except for the non-conductive layers.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: September 6, 2016
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Byung Jun Jeon, Byoung Hwa Lee, Hyun Hee Gu, Chang Hoon Kim, Young Ghyu Ahn
  • Patent number: 9438018
    Abstract: A junction box includes a box body, an upper cover, and a side cover. The box body has a side wall portion, an electric distribution portion, and a drain hole which is located at the inside of the side wall portion. The upper cover has a top panel and a down wall portion which are downwardly provided from the peripheral end of the top panel. The side cover has a terminal connected to the electric distribution portion and a case portion which covers the terminal. A drain groove is provided on an upper face of the case portion along the side wall portion. A downward slope is formed towards the drain hole on a bottom face of the drain groove.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: September 6, 2016
    Assignee: YAZAKI CORPORATION
    Inventors: Nobutaka Kaneko, Hiroki Tashiro
  • Patent number: 9439287
    Abstract: A structure for wireless communication having a plurality of conductor layers, an insulator layer separating each of the conductor layers, and at least one connector connecting two of the conductor layers wherein an electrical resistance is reduced when an electrical signal is induced in the resonator at a predetermined frequency.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: September 6, 2016
    Assignee: NuCurrent, Inc.
    Inventors: Vinit Singh, Christine A. Frysz
  • Patent number: 9437938
    Abstract: In a connecting method of a pressure attaching terminal to an electric wire, the pressure attaching terminal includes first and second electric wire connecting parts having U shapes and having a bottom plate part and one pairs of electric wire caulking pieces. When the electric wire is a single core electric wire, a single core conductor is set and one pairs of electric wire caulking pieces are respectively bent inside to caulk the caulking pieces to the single core conductor. When the electric wire is a multi-core electric wire as a multi-core twisted conductor, the multi-core conductor is set, and the one pair of electric wire caulking pieces are bent inside to caulk the electric wire caulking pieces to the multi-core conductor, and the one pair of electric wire caulking pieces are bent inside to caulk the electric wire caulking pieces to the part covered with a coat.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: September 6, 2016
    Assignee: YAZAKI CORPORATION
    Inventor: Kentaro Ohnuma
  • Patent number: 9433084
    Abstract: Methods of backdrilling printed circuit boards (PCBs) to remove via stubs and related apparatuses. The method may include removing a via stub through a combination of backdrilling and chemical etching. The backdrilling may remove a masking layer from the via stub. Portions of an underlying layer may remain in the region of the via stub after the backdrilling is completed. The remaining portions of the underlying layer may be removed in a subsequent etching process thereby removing the via stub from the PCB. As the backdrilling step may be used for the limited purpose of removing the outer layer and portions of the underlying layer remaining in the via can be tolerated, the diameter of the backdrilling need not be as large as traditional backdrilling where all layers within the via must be ensured of being completely removed.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: August 30, 2016
    Assignee: Flextronics AP, LLC
    Inventor: Cheuk Ping Lau