Patents Examined by Gustavo Ramallo
  • Patent number: 10199423
    Abstract: A complementary metal oxide semiconductor (CMOS) image sensor is provided that includes a substrate including a first surface, a second surface facing the first surface, and a first recess region that is recessed from the first surface toward the second surface. The CMOS image sensor further includes a transfer gate on the substrate, and a source follower gate on the first recess region. The source follower gate is within the first recess region and partially covers a portion of the first surface of the substrate.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: February 5, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hisanori Ihara, Jungchak Ahn
  • Patent number: 10153384
    Abstract: A contact region for a semiconductor substrate is disclosed. Embodiments can include forming a seed metal layer having an exposed solder pad region on the semiconductor substrate and forming a first metal layer on the seed metal layer. In an embodiment, a solderable material, such as silver, can be formed on the exposed solder pad region prior to forming the first metal layer. Embodiments can include forming a solderable material on the exposed solder pad region after forming the first metal layer. Embodiments can also include forming a plating contact region on the seed metal layer, where the plating contact region allows for electrical conduction during a plating process.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: December 11, 2018
    Assignee: SunPower Corporation
    Inventor: Thomas Pass
  • Patent number: 10153402
    Abstract: A light-emitting element includes a semiconductor light-emitting stack including a first semiconductor layer, an active layer, and a second semiconductor layer; a first conductive layer disposed on the second semiconductor layer and electrically connecting the second semiconductor layer; a second conductive layer disposed on the second semiconductor layer and electrically connecting the first semiconductor layer; and a cushion part disposed on the semiconductor light-emitting stack; wherein in a top view, the cushion part is disposed in a center region of the light-emitting element.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: December 11, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Tsung-Hsun Chiang, Chien-Chih Liao, Wen-Hung Chuang, Min-Yen Tsai, Bo-Jiun Hu
  • Patent number: 10153240
    Abstract: Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise a seed layer above a passivation layer, covering an opening of the passivation layer, and covering and in contact with a contact pad. A RDL is formed above the passivation layer, above and in contact with the seed layer, covering the opening of the passivation layer, and electrically connected to the contact pad through the seed layer. The RDL has an end portion with a surface that is smooth without a right angle. The surface of the end portion of the RDL may have an obtuse angle, or a curved surface.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: December 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Lin Lu, Hsien-Wei Chen, Kai-Chiang Wu, Hung-Jui Kuo
  • Patent number: 10153377
    Abstract: The present disclosure proposes a dual-gate thin film transistor and manufacturing method thereof and an array substrate. A manufacturing method includes: forming a first gate electrode, a gate insulating layer, a semiconductor layer, and an etch stop layer on a first substrate sequentially; forming a drain electrode, an independent electrode, and a source electrode on the exposed semiconductor layer; forming an insulating passivation layer on surfaces of the exposed etch stop layer, the drain electrode, the source electrode, and the independent electrode; and forming a second gate electrode on the insulating passivation layer in an area corresponding to the first gate electrode. The present disclosure can resolve the leakage current problem caused by the effective channel length between the source electrode and the drain electrode to improve the electrical properties of the dual-gate thin film transistor and improve its stability. The present disclosure can simplifies processes and reduce cost.
    Type: Grant
    Filed: December 25, 2015
    Date of Patent: December 11, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Hejing Zhang
  • Patent number: 10134943
    Abstract: A method for producing a multiplicity of semiconductor chips (13) is provided, comprising the following steps: —providing a wafer (1) comprising a multiplicity of semiconductor bodies (2), wherein separating lines (9) are arranged between the semiconductor bodies (2), —depositing a contact layer (10) on the wafer (1), wherein the material of the contact layer (10) is chosen from the following group: platinum, rhodium, palladium, gold, and the contact layer (10) has a thickness of between 8 nanometers and 250 nanometers, inclusive, —applying the wafer (1) to a film (11), —at least partially severing the wafer (1) in the vertical direction along the separating lines (9) or introducing fracture nuclei (12) into the wafer (1) along the separating lines (9), and —breaking the wafer (1) along the separating lines (9) or expanding the film (11) such that a spatial separation of the semiconductor chips (13) takes place, wherein the contact layer (10) is also separated.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: November 20, 2018
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Bernd Barchmann, Fabian Eigenmann, Andreas Ploessl
  • Patent number: 10134925
    Abstract: The present invention provides a thick-film paste composition for printing the front side of a solar cell device having one or more insulating layers. The thick-film paste comprises an electrically conductive metal and a dual-frit oxide composition dispersed in an organic medium.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: November 20, 2018
    Assignee: E I DU PONT DE NEMOURS AND COMPANY
    Inventors: Kenneth Warren Hang, Kathryn Lynn Goetschius, Yusuke Tachibana, Paul Douglas Vernooy
  • Patent number: 10121900
    Abstract: A thin-film transistor, a liquid crystal display panel, and a thin-film transistor manufacturing method are provided. The thin-film transistor includes a base plate and a gate electrode, a gate insulation layer, a source electrode, a drain electrode, a channel layer, first and second ohmic contact layers, a passivation layer, and a pixel electrode that are arranged on the same side of the base plate. The gate insulation layer covers the gate electrode that is on the base plate. The source electrode, the drain electrode, the channel layer, the first and second ohmic contact layers are arranged on the gate insulation layer. The channel layer is arranged between the source electrode and the drain electrode and corresponds to the gate electrode. The first ohmic contact layer is arranged between the source electrode and the channel layer. The second ohmic contact layer is arranged between the drain electrode and the channel layer.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: November 6, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Xiaobo Hu
  • Patent number: 10115930
    Abstract: OLED structures including an internal extraction layer are provided. The internal extraction layer includes a material having a refractive index that is higher than the refractive index of a transparent electrode in the device, and a non-planar interface disposed between the material and the substrate. Devices are also provided that include an external extraction layer having a non-planar surface which, when used in conjunction with an internal extraction layer, provides greatly improved outcoupling of light generated by the device.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: October 30, 2018
    Assignees: Universal Display Corporation, Kent State University
    Inventors: Yue Cui, Deng-ke Yang, Gregory McGraw, Ruiqing Ma, Julia J. Brown
  • Patent number: 10109674
    Abstract: A method of fabrication of a device includes forming a first metallization layer that is coupled to a logic device of the device. The method further includes forming a second metallization layer that is coupled to a magnetoresistive random access memory (MRAM) module of the device. The second metallization layer is independent of the first metallization layer.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: October 23, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Yu Lu, Seung Hyuk Kang
  • Patent number: 10109526
    Abstract: Structures for a skip via and methods of forming a skip via in an interconnect structure. A metallization level is formed that includes a dielectric layer with a top surface. An opening is formed that extends vertically from the top surface of the dielectric layer into the dielectric layer. A dielectric cap layer is deposited on a bottom surface of the opening. A fill layer is formed inside the opening and extends from the top surface of the dielectric layer to the dielectric cap layer on the bottom surface of the opening. A via opening is etched that extends vertically through the fill layer to the dielectric cap layer on the bottom surface of the opening.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 23, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Nicholas V. LiCausi, J. Jay McMahon, Ryan S. Smith, Errol Todd Ryan, Shao Beng Law
  • Patent number: 10096772
    Abstract: Embodiments of the present invention describe a method for fabricating a memory device comprising an enlarged space between neighboring bottom electrodes comprising depositing a poly-silicon layer on a substrate depositing a carbon layer above the poly-silicon layer, patterning a photo-resist layer on the carbon layer, depositing a first spacer layer on the photo-resist layer and performing a modified photolithography process on the photo resist layer after etching back the spacer layer creating sidewalls.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: October 9, 2018
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Jun Okuno
  • Patent number: 10062675
    Abstract: Micro-LED array display devices are disclosed. One of the micro-LED display devices includes: a micro-LED panel including a plurality of micro-LED pixels; a CMOS backplane including a plurality of CMOS cells corresponding to the micro-LED pixels to individually drive the micro-LED pixels; and bumps electrically connecting the micro-LED pixels to the corresponding CMOS cells in a state in which the micro-LED pixels are arranged to face the CMOS cells. The micro-LED pixels are flip-chip bonded to the corresponding CMOS cells formed on the CMOS backplane through the bumps so that the micro-LED pixels are individually controlled.
    Type: Grant
    Filed: June 4, 2017
    Date of Patent: August 28, 2018
    Assignee: LUMENS CO., LTD.
    Inventors: HanBeet Chang, EunSung Shin, HyunYong Cho
  • Patent number: 10062802
    Abstract: A method of manufacturing an embedded LED circuit board, including the step of: forming a through hole in a circuit substrate, the through hole communicating a first surface and a second surface of the circuit substrate; embedding a LED in the through hole of the circuit substrate; and electrically connecting two pins of the LED with a circuit disposed on the second surface of the circuit substrate. Because the LED is disposed in the through hole of the circuit substrate, not disposed on the surface on the circuit substrate, the LED is embedded in the circuit substrate. Therefore, the thickness of the embedded LED circuit board is reduced and it is advantageous to assembling the embedded LED circuit board in the electronic devices having limited volume.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: August 28, 2018
    Assignee: LONGMEN GETMORE POLYURETHANE CO., LTD.
    Inventor: Chia-Yen Lin
  • Patent number: 10056427
    Abstract: An FSI image sensor device structure is provided. The FSI image sensor device structure includes a substrate and a barrier structure formed in the substrate. The barrier structure includes a plurality of protrusion portions and a plurality of pillar portions. Each of the protrusion portions has a first height, and each of the pillar portions has a second height that is greater than the first height. The FSI image sensor device structure includes a pixel region formed over the protrusion portions and a storage region formed over the protrusion portions, wherein the pillar portions surround the pixel region.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 21, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ji-Heng Jiang, Ming-Chi Wu, Chi-Yuan Wen, Chien-Nan Tu, Yu-Lung Yeh
  • Patent number: 10043909
    Abstract: A semiconductor device with a high-quality epitaxial layer and a method of manufacturing the same. The semiconductor device may include: a substrate; a fin-shaped first semiconductor layer spaced apart from the substrate; a second semiconductor layer at least partially surrounding a periphery of the first semiconductor layer; an isolation layer formed on the substrate, exposing at least a part of the second semiconductor layer, wherein the exposed part of the second semiconductor layer extends in a fin shape; and a gate stack formed on the isolation layer and intersecting the second semiconductor layer.
    Type: Grant
    Filed: December 4, 2016
    Date of Patent: August 7, 2018
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 10032791
    Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: July 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Sup Lee, Sung-Hun Lee, Joonhee Lee, Seong Soon Cho
  • Patent number: 10033015
    Abstract: For a flexible, optically clear display stack, an adhesive, a system, and a method are provided. The adhesive is formed of polymer chains, at least a portion of which are cross-linked, a non-volatile diluent having a volume % in the range of between about 40 and 95, and is characterized with a low shear modulus of less than 10 kPa. The system is formed by at least first and second optically clear thin films with the adhesive disposed between the first and second thin films. The method includes the steps to form the system.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: July 24, 2018
    Assignee: Motorola Mobility LLC
    Inventors: Richard Brotzman, Deborah M. Paskiewicz
  • Patent number: 10008499
    Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: June 26, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kwan-Yong Lim, James Walter Blatchford, Shashank S. Ekbote, Younsung Choi
  • Patent number: 10008636
    Abstract: A light-emitting device is provided. comprises: a light-emitting stack comprising an active layer emitting a first light having a first peak wavelength ? nm; and an adjusting element stacked on and electrically connected to the active layer, wherein the adjusting element comprises a diode emitting a second light having a second peak wavelength between 800 nm and 1900 nm; wherein a forward voltage of the light-emitting device is between (1240/0.8?) volt and (1240/0.5?) volt, and a ratio of the intensity of the first light emitted from the active layer at the first peak wavelength to the intensity of the second light emitted from the diode at the second peak wavelength is greater than 10 and not greater than 1000.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: June 26, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Chih-Chiang Lu, Yi-Chieh Lin, Rong-Ren Lee, Yu-Ren Peng, Ming-Siang Huang, Ming-Ta Chin, Yi-Ching Lee