Abstract: A silicon carbide (SiC) semiconductor device, including a SiC substrate, a first SiC layer formed on the substrate, first and second impurity layers selectively formed in the first SiC layer, a second SiC layer formed on the first SiC layer, a third impurity layer selectively formed in the second SiC layer and on the second impurity layer, a third SiC layer formed on the second SiC layer, a fourth impurity layer selectively formed in the third SiC layer, a trench that penetrates the fourth impurity layer and the second and third SiC layers, a bottom thereof reaching the first impurity layer, and a gate electrode formed in the trench via a gate insulating film. The first SiC layer has first and second regions adjacent respectively to the first and second impurity layers on a side facing the substrate, an impurity concentration at the first region being lower than that at the second region.

Abstract: According to one embodiment, a semiconductor memory device includes first and second interconnect parts, and a second interconnect connection part. The first interconnect part includes a first core part, and a first interconnect layer. The first interconnect layer includes a first surrounding region and a first extended region. The second interconnect part includes a second core part, and a second interconnect layer. The second interconnect layer includes a second surrounding region and a second extended region. The second extended connection part overlaps a part of the first extended region in the third direction, overlaps the second core part in the first direction, and is electrically connected to the second core part. The second extended surrounding part is provided around the second extended connection part and contains a material contained in the first surrounding region.

Abstract: The present invention discloses an array substrate, comprising a first storage capacitor and a second storage capacitor, and the first storage capacitor and the second storage capacitor are coupled in parallel to form a total storage capacitor of the array substrate to increase the total storage capacitor of the array substrate, so as to avoid the issues of the cross talk and the image residue due to the over small total storage capacitor for promoting the quality of the array substrate. The present invention further discloses a display panel utilizing the array substrate and a liquid crystal display panel utilizing the array substrate.

Abstract: A method of reducing defects in an epitaxial layer. The method includes forming one or more barrier structures within a peripheral edge region of a wafer substrate, and forming an epitaxial layer over a surface of the wafer substrate.

Abstract: A method of fabricating a nonpolar gallium nitride-based semiconductor layer is provided. The method is a method of fabricating a nonpolar gallium nitride layer using metal organic chemical vapor deposition, and includes disposing a gallium nitride substrate with an m-plane growth surface within a chamber, raising a substrate temperature to a GaN growth temperature by heating the substrate, and growing a gallium nitride layer on the gallium nitride substrate by supplying a Ga source gas, an N source gas, and an ambient gas into the chamber at the growth temperature. The supplied ambient gas contains N2 and does not contain H2.

Abstract: Application of a wavelength conversion element is substantially independent of the fabrication of a side-emitting light emitting device. In an example embodiment, the wavelength conversion element is situated around the periphery of a non-wavelength converting lightguide that is situated above the light emitting surface. One or more specular and/or diffusing reflectors are used to direct the light in the lightguide toward the wavelength conversion element at the periphery. In another embodiment, an interference filter may be used to provide predominantly side-emitted light at interfaces between the elements of the light emitting device.

Abstract: A Metal Oxide Thin Film Transistor (MOTFT) and a preparation method thereof are provided. The preparation method includes the following steps in turn: Step a: a metal conductive layer is prepared and patterned as a gate on a substrate; Step b: a first insulating thin film is deposited as a gate insulating layer on the metal conductive layer; Step c: a metal oxide thin film is deposited and patterned as an active layer on the gate insulating layer; Step d: an organic conductive thin film is deposited as a back channel etch protective layer on the active layer; Step e: a metal layer is deposited on the back channel etch protective layer and then patterned as pattern of a source electrode and a drain electrode; Step f: a second insulating thin film is deposited as a passivation layer on the source electrode and the drain electrode.

Abstract: Disclosed are a 3D display panel and the 3D display device. The 3D display panel includes a base plate, a plurality of pixel units, and first and second light emission units. Each of the pixel units includes at least one the sub-pixel, which includes primary and secondary pixel respectively corresponding to the first and second light emission units. Each of the two light emission units includes an anode, a hole transportation layer, an orientation layer, a light emissive layer, an electron transportation layer, and a cathode that are sequentially stacked. In the first and second light emission units, the orientation layers set the orientations of the light emissive layers to first and second orientation states, respectively, and first and second electrons and first and second holes respectively generated by the cathodes and anodes are recombined in the light emissive layers to respectively emit first and polarization light, which are orthogonal.

Abstract: In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium.

Abstract: The invention relates to a process for producing a composite body (36) having at least one functional layer or for the further use for producing an electronic or optoelectronic component (40, 42, 44). The composite body (36) is in the form of a layer structure and comprises at least one substrate (34), which is in the form of a plate and has at least one planar substrate surface, and at least one substantially polycrystalline or at least one substantially single-crystal layer (38), which comprises at least one compound semiconductor, a ceramic material or a metallic hard material. The process is characterized by the following steps: heating at least part of the planar substrate surface to a temperature of at least 100° C. and at most 550° C.

Abstract: Provided is a method for creating a mask blank that includes a capping layer and a shifter layer. The capping layer is optically compatible and process compatible with the shifter layer. The method may include providing a cleaned and polished mask substrate to a deposition tool and depositing, within the deposition tool, a shifter layer over a cleaned and polished mask substrate. The shifter layer may include each material of a set of materials in a first proportion. The method may also include depositing an additional layer over the shifter layer, the additional layer providing a capping layer over the shifter layer. The capping layer includes the materials in a second proportion unequal to the first proportion. The capping layer includes molybdenum, silicon, and nitride in a proportion that aids in detection by a residual gas analyzer. Also provided is also a mask blank structure incorporating the compatible capping layer.

Abstract: A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface.

Abstract: A semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a conductor over the conductive pad. The semiconductor device further has a molding compound surrounding the semiconductor substrate, the conductive pad and the conductor. In the semiconductor device, the conductor has a stud shape.

Abstract: An electronic package includes a lead frame structure having one or more structural features configured to improve board level reliability. In one embodiment, the structural feature comprises lead frame protrusions extending outward from the electronic package, which are configured to laterally engage solder structures used to attach the electronic package to a next level of assembly. In another embodiment, conductive bumps are attached to exposed portions of the lead frame in advance of next level assembly processes. In a further embodiment, the lead frame comprises laterally separated contact points for attaching an electron die and for attaching the electronic package to a next level of assembly.

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. A source conductive line structure is provided between the substrate and the alternating stack. The source conductive line structure includes a plurality of parallel conductive rail structures extending along a same horizontal direction and adjoined to a common conductive straddling structure. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support matrix. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure and the support matrix.

Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors are described. The memory cell includes a substrate having a non-volatile memory (NVM) region and a plurality of metal-oxide-semiconductor (MOS) regions. A NVM transistor in the NVM region includes a tunnel dielectric on the substrate, a charge-trapping layer on the tunnel dielectric, and a blocking dielectric comprising a high-k dielectric material over the charge-trapping layer. The plurality of MOS regions include a number of MOS transistors. At least one of the MOS transistors includes a gate dielectric comprising a high-k dielectric material over a surface of the substrate. Generally, the blocking dielectric and the gate dielectric comprise the same high-k dielectric material. Other embodiments are also described.

Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.

Abstract: A semiconductor device includes a light emitting structure, and an interconnection bump including an under bump metallurgy (UBM) layer disposed on an electrode of at least one of the first and second conductivity-type semiconductor layers, and having a first surface disposed opposite to a surface of the electrode and a second surface extending from an edge of the first surface to be connected to the electrode, an intermetallic compound (IMC) disposed on the first surface of the UBM layer, a solder bump bonded to the UBM layer with the IMC therebetween, and a barrier layer disposed on the second surface of the UBM layer and substantially preventing the solder bump from being diffused into the second surface of the UBM layer.

Abstract: Techniques are disclosed for methods of post-treating an etch stop or a passivation layer in a thin film transistor to increase the stability behavior of the thin film transistor.

Abstract: Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors are described. The memory cell includes a substrate having a non-volatile memory (NVM) region and a plurality of metal-oxide-semiconductor (MOS) regions. A NVM transistor in the NVM region includes a tunnel dielectric on the substrate, a charge-trapping layer on the tunnel dielectric, and a blocking dielectric comprising a high-k dielectric material over the charge-trapping layer. The plurality of MOS regions include a number of MOS transistors. At least one of the MOS transistors includes a gate dielectric comprising a high-k dielectric material over a surface of the substrate. Generally, the blocking dielectric and the gate dielectric comprise the same high-k dielectric material. Other embodiments are also described.