Abstract: A method and structure comprise a field effect transistor structure that includes a first rectangular fin structure and a second rectangular fin structure, both positioned on a substrate. The sides of the second rectangular fin structure are parallel to the sides of the first rectangular fin structure. Further, a trench insulator is positioned on the substrate and positioned between a side of the first rectangular fin structure and a side of the second rectangular fin structure. A gate conductor is positioned on the trench insulator, positioned over the sides and the top of the first rectangular fin structure, and positioned over the sides and the top of the second rectangular fin structure. The gate conductor runs perpendicular to the sides of the first rectangular fin structure and the sides of the second rectangular fin structure. Also, a gate insulator is positioned between the gate conductor and the first rectangular fin structure and between the gate conductor and the second rectangular fin structure.

Abstract: An organic EL device 1, for example, excellent in productivity and performance with reduced influence of a voltage drop can be provided at low fabrication cost. The organic EL device 1 includes band-shaped organic EL strips 3 arranged at spacings on a first substrate 2. Each of the organic EL strips 3 includes a second substrate 31, a negative electrode 32b, a positive electrode 32a, and an organic layer 33. The pair of the electrodes 32a and 32b and the organic layer 33 are stacked on the second substrate 2 with the organic layer 33 sandwiched between the electrodes 32a and 32b. The first substrate 2 includes a connection terminal electrode 5 and an auxiliary terminal electrode 6. For example, negative electrode 32b is electrically connected to the connection terminal electrode 5, and the positive electrode 32a is electrically connected to the auxiliary terminal electrode 6.

Abstract: A semiconductor device production method includes: forming a semiconductor region including a first region, a second region connecting with the first region and having a width smaller than that of the first region, and a third region connecting with the second region and having a width smaller than that of the second region; forming a gate electrode including a first part crossing the third region and a second part extending from the first part across the first region; forming a side wall insulation film on the gate electrode to cover part of the second region while exposing the remaining part of the second region; implanting a second conductivity type impurity into the first region and the remaining part of the second region; performing heat treatment; removing part of the side wall insulation film, and forming a silicide layer on the first region and the remaining part of the second region.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, a two-dimensional carrier gas layer, a first main electrode, a second main electrode, a first gate electrode, and a second gate electrode. The first gate electrode is provided between a part of the first main electrode and a part of the second main electrode opposite to the part of the first main electrode. The second gate electrode is provided between another part of the first main electrode and another part of the second main electrode opposite to the another part of the first main electrode with a separation region interposed between the first gate electrode and the second gate electrode. The second gate electrode is controlled independently of the first gate electrode.

Abstract: The present invention relates to manufacturing technology of damascene copper interconnection in the semiconductor manufacturing field, and especially relates to a method to manufacture by trench-first copper interconnection. The method to manufacture trench-first copper interconnection forms metal trench and VIA hole structures in the photoresist which can form a hard mask through exposure and development processes, and then forms metal interconnection lines via etching metal trench and VIA hole in one etch process. The above method replaces the existing.

Abstract: According to one embodiment, a semiconductor device includes a source region having p-type conductivity, a drain region having p-type conductivity, a channel region provided between the source region and the drain region and having n-type conductivity, a lower gate insulating film provided on the channel region, a lower gate electrode provided on the lower gate insulating film, an upper gate insulating film provided on the lower gate electrode, an upper gate electrode provided on the upper gate insulating film, and a switching element connected between the lower gate electrode and the source region.

Abstract: A multi-die package includes a first semiconductor die and a second semiconductor die each having an upper surface with a plurality of bond pads positioned thereon. The multi-die package also includes a plurality of bonding wires each coupling one of the bond pads on the upper surface of the first semiconductor die to a corresponding one of the bond pads on the upper surface of the second semiconductor die. A bonding wire of the plurality of bonding wires includes a first portion extending upward from one of the second plurality of bond pads substantially along a z-axis and curving outward substantially along x and y axes in a direction towards the first semiconductor die. The bonding wire also includes a second portion coupled to the first portion and extending from the first portion downward to one of the first plurality of bond pads on the upper surface of the first semiconductor die.

Abstract: An isolation region (14) is formed between an edge termination region (2) having deep trenches (20,34) and the central region (4). The isolation region includes gate fingers (18) extending from the edge gate trench regions (28) to the gate trenches (6) in the central region (4) to electrically connect the edge gate trench regions to the gate trenches (6) in the central region. The isolation region also includes isolation fingers (22,24) extending from the edge termination region (2) towards the central region (4) and gate between the gate fingers (18) for reducing the breakdown voltage with a RESURF effect.

Abstract: An integrated circuit package system including: forming a die pad, wherein the die pad has a tiebar at a corner; forming a lead wherein the lead is connected to the tiebar; connecting an integrated circuit die to the die pad; and forming an encapsulation, having an edge, over the integrated circuit die with the lead extending from and beyond the edge.

Abstract: Manufacturing a semiconductor device with higher operating characteristics and achieve low power consumption of a semiconductor integrated circuit. A single crystal semiconductor layer is formed so that crystal plane directions of single crystal semiconductor layers which are used for channel regions of an n-channel and a p-channel TFT and which are formed over the same plane of the substrate are the most appropriate crystal plane directions for each TFT. In accordance with such a structure, mobility of carrier flowing through a channel is increased and the semiconductor device with higher operating characteristics can be provided. Low voltage driving can be performed, and low power consumption can be achieved.

Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, and a sealing member. The first semiconductor substrate has a surface and includes a sensing portion on the surface side. The sensing portion has a movable portion. The first semiconductor substrate and the second semiconductor substrate are bonded together to form a stacked substrate. The stacked substrate defines a hermetically sealed space for accommodating the sensing portion between the first and second semiconductor substrates. The stacked substrate further defines a recess extending between the first semiconductor substrate and the second semiconductor substrate to penetrate an interface between the first semiconductor substrate and the second semiconductor substrate. The sealing member is located in the recess.

Abstract: On a surface of a semiconductor substrate, a plurality of terraces formed stepwise by an atomic step are formed in the substantially same direction. Using the semiconductor substrate, a MOS transistor is formed so that no step exists in a carrier traveling direction (source-drain direction).

Abstract: A method of forming a three-dimensional electronic device includes forming at least one electronic device on a two-dimensional, flexible substrate, the electronic device being formed according to a three-dimensional structure, cutting the two-dimensional, flexible substrate, the cuts being located to allow the two-dimensional substrate to be shaped, the cuts having at least one stress relief feature, and shaping the two-dimensional, flexible substrate to form the three-dimensional structure, the stress relief features arranged to alleviate stress in the three-dimensional structure.

Abstract: A device having thin-film transistor (TFT) metal-oxide-nitride-oxide-semiconductor (MONOS) or semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell structures includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. The dielectric layer is associated with a first surface. Each of the one or more source or drain regions includes an N+ polysilicon layer on a diffusion barrier layer which is on a conductive layer. The N+ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P? polysilicon layer overlying the co-planar surface, an oxide-nitride-oxide (ONO) layer overlying the P? polysilicon layer; and at least one control gate overlying the ONO layer. The control gate may be made of a metal layer or a P+ polysilicon layer.

Abstract: Provided are spin field effect logic devices, the logic devices including: a gate electrode; a channel formed of a magnetic material above the gate electrode to selectively transmit spin-polarized electrons; a source on the channel; and a drain and an output electrode on the channel outputting electrons transmitted from the source. The gate electrode may control a magnetization state of the channel in order to selectively transmit the electrons injected from the source to the channel.

Abstract: A trench MOSFET layout with multiple trenched floating gates and at least one trenched channel stop gate in termination area shorted with drain region is disclosed to make it feasibly achieved after die sawing. The layout consisted of dual trench MOSFETs connected together with multiple sawing trenched gates across a space between the two trench MOSFETs having a width same as scribe line.

Abstract: An image display panel includes a gate electrode; a gate insulating film over the gate electrode; a source electrode, a drain electrode, and a first adhesive on the gate insulating film; an organic semiconductor layer on the source and drain electrodes including a space; an interlayer insulating film covering the gate insulating film, source electrode, organic semiconductor layer, and part of the drain electrode; a conductive layer on the interlayer insulating film; a second adhesive formed over the interlayer insulating film and conductive layer; an image display medium on the second adhesive; an inorganic film on the image display medium and first adhesive; and a second substrate on the inorganic film, where the first adhesive is arranged outside the second adhesive between the display medium and the conductive layer, and forms bonding between the inorganic film and the gate insulating film having a hydrophilic treatment formed on the first substrate.

Abstract: A semiconductor light emitting device includes a lower cladding layer, an active layer, and an AlGaAs upper cladding layer mounted on a GaAs substrate. The semiconductor light emitting device has a ridge structure including the AlGaAs upper cladding layer. The semiconductor light emitting device further includes an InGaAs etching stop layer provided in contact with the lower side of the AlGaAs upper cladding layer. The InGaAs etching stop layer has a band gap greater than that of the active layer.

Abstract: The present invention provides a condenser microphone capable of detecting small sounds (e.g., Korotkoff sounds) with high sensitivity even in environments with variations in pressure, such as cuff pressure. A condenser microphone (10) is disposed as an acoustic sensor for detecting Korotkoff sounds in a communication space reachable by the internal pressure of the cuff of a blood pressure gauge. In the condenser microphone, a diaphragm (13) and a backplate 14) are disposed in the interior of a housing (11), an aeration hole (30) is formed in a wall (11B) that blocks off the housing back surface, and a sound-absorbing element (20) having sound absorption characteristics with respect to a frequency band targeted for detection is disposed on the front surface of a housing (11).

Abstract: A surface mountable package includes a base and a cover with a cavity defined thereby, and an acoustic transducer unit received in the cavity. The cover includes a first metal ring to enclose the acoustic transducer unit. The base includes a second metal ring to press against the first metal ring in order to form a metal shielding area. First and second metal connecting paths are formed electrically connected to the metal shielding area and the acoustic transducer unit, respectively. Besides, two pairs of first and second surface mountable metal electrodes are electrically connected to the first and the second metal connecting paths, respectively. As a result, the package can be selectively double surface mountable to a user's circuit board via the metal electrodes of the base or the metal electrodes of the cover.