Abstract: The present invention discloses a vertical SOI bipolar junction transistor and a manufacturing method thereof. The bipolar junction transistor includes an SOI substrate from down to up including a body region, a buried oxide layer and a top silicon film; an active region located in the top silicon film formed by STI process; a collector region located in the active region deep close to the buried oxide layer formed by ion implantation; a base region located in the active region deep close to the top silicon film formed by ion implantation; an emitter and a base electrode both located over the base region; a side-wall spacer located around the emitter and the base electrode. The present invention utilizing a simple double poly silicon technology not only can improve the performance of the transistor, but also can reduce the area of the active region in order to increase the integration density.

Abstract: A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow.

Abstract: An organic electroluminescence display device includes a pixel isolating film that is provided over a substrate and has a plurality of apertures, and a plurality of pixels provided corresponding to the plurality of apertures. Each of the plurality of pixels has a first electrode, a functional layer including at least an organic light emitting layer, and a second electrode sequentially from the side of the substrate, and part or whole of the first electrode is separate from an edge part of the aperture on the side of the substrate.

Abstract: An interconnect sensor for detecting delamination due to coefficient of thermal expansion mismatch and/or mechanical stress. The sensor comprises a conductive path that includes a via disposed between two back end of line metal layers separated by a dielectric. The via is coupled between a first probe structure and a second probe structure and mechanically coupled to a stress inducing structure. The via is configured to alter the conductive path in response to mechanical stress caused by the stress inducing structure. The stress inducing structure can be a through silicon via or a solder ball. The dielectric material can be a low-k dielectric material. In another embodiment, a method of forming an interconnect sensor is provided for detecting delamination.

Abstract: Disclosed herein is a solid-state imaging device including: an opto-electrical conversion section provided inside a semiconductor substrate to receive incident light coming from one surface of the semiconductor substrate; a wiring layer provided on the other surface of the semiconductor substrate; and a light absorption layer provided between the other surface of the semiconductor substrate and the wiring layer to absorb transmitted light passing through the opto-electrical conversion section as part of the incident light.

Abstract: A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a substrate; a nitride based compound semiconductor layer placed on the substrate and doped with a first transition metal atom; an aluminum gallium nitride layer (AlxGa1-xN) (where 0.1<=x<=1) placed on the nitride based compound semiconductor layer; a nitride based compound semiconductor layer placed on the aluminum gallium nitride layer (AlxGa1-xN) (where 0.1<=x<=1) and doped with a second transition metal atom; an aluminum gallium nitride layer (AlyGa1-yN) (where 0.1<=y<=1) placed on the nitride based compound semiconductor layer doped with the second transition metal atom; and a gate electrode, a source electrode, and a drain electrode which are placed on the aluminum gallium nitride layer (AlyGa1-yN) (where 0.1<=y<=1).

Abstract: A light emitting device containing a semiconductor light emitting component and a phosphor, the phosphor is capable of absorbing a part of light emitted by the light emitting component and emitting light of a wavelength different from that of the absorbed light, is provided. A straight line connecting a point of chromaticity corresponding to a spectrum generated by the light emitting component and a point of chromaticity corresponding to a spectrum generated by the phosphor is substantially along a black body radiation locus in a chromaticity diagram.

Abstract: A resistive memory element comprising a conductive material, an active material over the conductive material, and an ion source material on the active material and comprising at least one chalcogen, at least one active metal, and at least one additional element. Additional resistive memory elements, as well as methods of forming resistive memory elements, and related resistive memory cells and resistive memory devices are also described.

Abstract: A semiconductor device includes a semiconductor chip, a connection electrode including a first land electrode electrically coupled with the semiconductor chip, and a through electrode formed on an upper surface of the first land electrode to be electrically coupled with the first land electrode using a stud bump, and a sealing resin, through which the connection electrode passes, for sealing the semiconductor chip.

Abstract: A photodetector with internal gain comprising a semiconductor structure in which impact ionization events are produced mostly by minority charge carriers; a first biasing contact and a second biasing contact located in the semiconductor structure; a means of defining, in the semiconductor structure, a photon collection region close to first biasing contact; a P-N type junction formed in the semiconductor structure between the two biasing contacts and close to the second biasing contact; and a collector contact which is located in the P-N junction and used to collect current in the P-N junction.

Abstract: Embodiments of the invention are directed to an IR photodetector that broadly absorbs electromagnetic radiation including at least a portion of the near infrared (NIR) spectrum. The IR photodetector comprises polydispersed QDs of PbS and/or PbSe. The IR photodetector can be included as a layer in an up-conversion device when coupled to a light emitting diode (LED) according to an embodiment of the invention.

Abstract: A fabricating method of integrated circuit is provided. During the fabricating process of an interconnecting structure of the integrated circuit, a micro electromechanical system (MENS) diaphragm is formed between two adjacent dielectric layers of the interconnecting structure. The method of forming the MENS diaphragm includes the following steps. Firstly, a plurality of first openings is formed within any dielectric layer to expose corresponding conductive materials of the interconnecting structure. Secondly, a bottom insulating layer is formed on the dielectric layer and filling into the first openings. Third, portions of the bottom insulating layer located in the first openings are removed to form at least a first trench for exposing the corresponding conductive materials. Then, a first electrode layer and a top insulating layer are sequentially formed on the bottom insulating layer, and the first electrode layer filled into the first trench and is electrically connected to the conductive materials.

Abstract: An electroless Cu layer is formed on each side of a packaging substrate containing a core, at least one front metal interconnect layer, and at least one backside metal interconnect layer. A photoresist is applied on both electroless Cu layers and lithographically patterned. First electrolytic Cu portions are formed on exposed surfaces of the electroless Cu layers, followed by formation of electrolytic Ni portions and second electrolytic Cu portions. The electrolytic Ni portions provide enhanced resistance to electromigration, while the second electrolytic Cu portions provide an adhesion layer for a solder mask and serves as an oxidation protection layer. Some of the first electrolytic Cu may be masked by lithographic means to block formation of electrolytic Ni portions and second electrolytic Cu portions thereupon as needed. Optionally, the electrolytic Ni portions may be formed directly on electroless Cu layers.

Abstract: A semiconductor device includes a channel region; a gate dielectric over the channel region; and a gate electrode over the gate dielectric. A first source/drain region is adjacent the gate dielectric, wherein the first source/drain region is a semiconductor region and of a first conductivity type. A second source/drain region is on an opposite side of the channel region than the first source/drain region, wherein the second source/drain region is a metal region. A pocket region of a second conductivity type opposite the first conductivity type is horizontally between the channel region and the second source/drain region.

Abstract: A method of forming an integrated circuit structure includes providing a wafer having a first semiconductor chip, a second semiconductor chip, and a scribe line between and adjoining the first semiconductor chip and the second semiconductor chip; forming a notch in the scribe line, wherein the notch has a bottom no higher than a top surface of a semiconductor substrate in the wafer; forming a first insulation film over the wafer, wherein the first insulation film extends into the notch; removing a portion of the first insulation film from a center of the notch, wherein a remaining portion of the first insulation film comprises an edge in the notch; and sawing the wafer to separate the first semiconductor chip and the second semiconductor chip.

Abstract: The present approach involves a radiation detector module with increased quantum efficiency and methods of fabricating the radiation detector module. The module includes a scintillator substrate and a photodetector fabricated on the scintillator substrate. The photodetector includes an anode, active organic elements, and a cathode. The module also includes a pixel element array disposed over the photodetector. During imaging, radiation attenuated by an object to be imaged may propagate through the pixel element array and through the layers of the photodetector to be absorbed by the scintillator which in response emits optical photons. The photodetector may absorb the photons and generate charge with improved quantum efficiency, as the photons may not be obscured by the cathode or other layers of the module. Further, the module may include reflective materials in the cathode and at the pixel element array to direct optical photons towards the active organic elements.

Abstract: A first AlGaN layer formed over a substrate, a second AlGaN layer formed over the first AlGaN layer, an electron transit layer formed over the second AlGaN layer, and an electron supply layer formed over the electron transit layer are provided. A relationship of “0?x1<x2?1” is found when a composition of the first AlGaN layer is represented by Alx1Ga1-x1N, and a composition of the second AlGaN layer is represented by Alx2Ga1-x2N. Negative charges exist at an upper surface of the AlGaN layer more than positive charges existing at a lower surface of the AlGaN layer.

Abstract: A semiconductor device comprises an active layer above a first confinement layer. The active layer comprises a layer of ?-Sn less than 20 nm thick. The first confinement layer is formed of material with a wider band gap than ?-Sn, wherein the band gap offset between ?-Sn and this material allows confinement of charge carriers in the active layer so that the active layer acts as a quantum well. A similar second confinement layer may be formed over the active layer. This semiconductor device may be a p-FET. A method of fabricating such a semiconductor device is described.

Abstract: A bidirectional switch includes a plurality of unit cells 11 including a first ohmic electrode 15, a first gate electrode 17, a second gate electrode 18, and a second ohmic electrode 16. The first gate electrodes 15 are electrically connected via a first interconnection 31 to a first gate electrode pad 43. The second gate electrodes 18 are electrically connected via a second interconnection 32 to a second gate electrode pad 44. A unit cell 11 including a first gate electrode 17 having the shortest interconnect distance from the first gate electrode pad 43 includes a second gate electrode 18 having the shortest interconnect distance from the second gate electrode pad 44.

Abstract: A semiconductor device with a semiconductor body and method for its production is disclosed. The semiconductor body includes drift zones of epitaxially grown semiconductor material of a first conduction type. The semiconductor body further includes charge compensation zones of a second conduction type complementing the first conduction type, which are arranged laterally adjacent to the drift zones. The charge compensation zones are provided with a laterally limited charge compensation zone doping, which is introduced into the epitaxially grown semiconductor material. The epitaxially grown semiconductor material includes 20 to 80 atomic % of the doping material of the drift zones and a doping material balance of 80 to 20 atomic % introduced by ion implantation and diffusion.