Abstract: A semiconductor device includes a first die connected to a first channel, the first die comprising a first memory chip; and a second die connected to a second channel, the second die comprising a second memory chip, the first and second channels being independent of each other and a storage capacity and a physical size of the second die being the same as those of the first die. The first and second dies are disposed in one package, and the package includes an interconnection circuit disposed between the first die and the second die to transfer signals between the first memory chip and the second memory chip.
July 3, 2017
Date of Patent:
September 17, 2019
SAMSUNG ELECTRONICS CO., LTD.
Jaehyung Lee, JungSik Kim, Youngdae Lee, Duyeul Kim, Sungmin Yim, Kwangil Park, Chulsung Park
Abstract: A bit line power supply apparatus including a bit line high voltage generator is provided. The bit line high voltage generator includes a first voltage generation circuit and a second voltage generation circuit. The first voltage generation circuit includes a first sensor and a first linear voltage regulator. The first sensor compares a first reference voltage with a bit line high voltage to generate a first sensing voltage according to a first control signal. The first linear regulator generates the bit line high voltage according the first sensing voltage. The second voltage generation circuit includes a second sensor and a switching voltage regulator. The second sensor compares the first reference voltage with the bit line high voltage to generate a second sensing voltage according to a second control signal. The switching regulator generates the bit line high voltage according the second sensing voltage.
Abstract: A memory system comprising: a memory device including a plurality of memory dies each having a plurality of the memory blocks; and a controller suitable for performing a command operation to the memory dies, wherein the memory device comprises means for performing an error check operation to a first data provided from the controller to store the first data the memory device.
Abstract: Methods, systems, and devices for a pulsed integrator and memory techniques are described. A first device may facilitate discharging a memory cell using at least one current pulse until a voltage associated with the memory cell reaches a reference voltage. The discharge time of the memory cell may be determined based at least in part on a duration of at least one current pulse. In some examples, a state of the memory cell may be determined based at least in part on a discharge time.
Abstract: Systems and methods are described for predicting potential failures in flash memory devices by probing for memory cells with marginal programming characteristics. A method includes receiving a write request. The method also includes applying a predetermined number of programming pulses to a plurality of memory cells within a block of a flash memory device. The method also includes applying a verify pulse to each respective one of the plurality of memory cells. The method also includes storing programming status of the plurality of memory cells into a set of latches. The method also includes determining, based on the stored programming status, a total number of memory cells within the block that fall outside of one or more predetermined expected ranges. The method also includes identifying the block as a block in risk when the total number of memory cells satisfies a predetermined risk threshold.
May 21, 2018
Date of Patent:
September 10, 2019
Western Digital Technologies, Inc.
Tomer Tzvi Eliash, Arthur Shulkin, James Yin Tom, Eran Sharon
Abstract: Methods, systems, and devices for operating an electronic memory apparatus are described. A logic value stored in a ferroelectric random access memory (FeRAM) cell is read onto a first sensing node of a sense amplifier. The reading is performed through a digit line coupling the FeRAM cell to the first sensing node, while the sense amplifier is in an inactive state. A second sensing node of the sense amplifier is biased to a reference voltage provided by a reference voltage source. The biasing is performed while reading the logic value stored in the FeRAM cell onto the first sensing node. The digit line is isolated from the first sensing node after the reading. The sense amplifier is activated, after isolating the digit line from the first sensing node, to amplify and sense a voltage difference between the first sensing node and the second sensing node.
Abstract: A field effect transistor, a memory element, and a manufacturing method of a charge storage structure are provided. The memory element includes a plurality of field effect transistors, and each of the field effect transistors includes a substrate, a source region, a drain region, a gate conductive layer, and a charge storage structure. Both the source region and the drain region are located in the substrate and connected to an upper surface of the substrate. The source and drain regions are spaced apart from each other to define a channel region therebetween. The gate conductive layer is disposed over the upper surface and overlaps with the channel region. The charge storage structure disposed between the gate conductive layer and the channel region includes a ferroelectric material and a paraelectric material so that the charge storage structure has better capability of trapping charges and a higher switching speed.
Abstract: A solid state drive (SSD) device includes a first nonvolatile memory package, a second nonvolatile memory package, and a controller. The first nonvolatile memory package includes a first buffer chip and a plurality of first nonvolatile memory chips. The second nonvolatile memory package includes a plurality of second nonvolatile memory chips. The controller controls the first nonvolatile memory package and the second nonvolatile memory package. The first buffer chip communicates a first address signal and a first data with the controller, and selectively communicates the first data with one of the plurality of first nonvolatile memory chips and the plurality of second nonvolatile memory chips based on the first address signal.
Abstract: In some aspects, a heterogeneous computing system includes a quantum processor unit and a classical processor unit. In some instances, variables defined by a computer program are stored in a classical memory in the heterogeneous computing system. The computer program is executed in the heterogeneous computing system by operation of the quantum processor unit and the classical processor unit. Instructions are generated for the quantum processor by a host processor unit based on values of the variables stored in the classical memory. The instructions are configured to cause the quantum processor unit to perform a data processing task defined by the computer program. The values of the variables are updated in the classical memory based on output values generated by the quantum processor unit. The classical processor unit processes the updated values of the variables.
October 25, 2018
Date of Patent:
September 3, 2019
Rigetti & Co, Inc.
Chad Tyler Rigetti, William J. Zeng, Dane Christoffer Thompson
Abstract: A memory apparatus may be provided. The memory apparatus may include a global bit line configured to receive a drift current. A voltage clamping circuit configured to limit a voltage level of the global bit line.
Abstract: A driver of a multi-level signaling interface is provided. The driver may be configured reduce noise in a multi-level signal (e.g., a pulse amplitude modulation signal) generated by the driver using switching components of different polarities. The driver may include a pull-up circuit and/or a pull-down circuit. The pull-up circuit and the pull-down circuit may include at least one switching component of a first polarity (e.g., nmos transistor) and at least one switching component of a second polarity different from the first polarity (e.g., pmos transistor). Such a configuration of pull-up and pull down circuits may generate a more linear relationship between an output current and an output voltage of an output of the driver, thereby improving one or more characteristics of the multi-level signal.
Abstract: A nonvolatile memory includes a plurality of memory blocks, a plurality of source drivers corresponding to the plurality of memory blocks, a plurality of pass transistor groups connected between the plurality of source drivers and the plurality of memory blocks, a plurality of block pass transistors connected between a plurality of block word lines and the plurality of pass transistor groups, a plurality of block decoders corresponding to a plurality of memory block groups respectively, and a block pass transistor decoder configured to control voltages of block select lines connected to the plurality of block pass transistors. The plurality of memory blocks are divided into the plurality of memory block groups. Each block decoder is configured to control voltages of block word lines, among the plurality of block word lines, connected to at least two memory blocks of a corresponding memory block group in common.
Abstract: An electronic device including a semiconductor memory may be provided. The semiconductor memory may include a write circuit configured for generating a first current. The semiconductor memory may include a first selection circuit configured for coupling the first write circuit to a first line based on a first selection signal. The semiconductor memory may include a second write circuit configured for generating a second current. The semiconductor memory may include a second selection circuit configured for coupling the second write circuit to a second line based on a second selection signal. The semiconductor memory may include a memory cell coupled between the first line and the second line. The semiconductor memory may include a voltage control circuit configured for controlling a voltage level of the second line.
Abstract: A double data rate memory includes a circuit board, a goldfinger connection interface, at least 16 first IC chips, at least 16 second IC chips, a first and a second read-only memory. The circuit board has a first surface, a second surface, a first region and a second region. The first IC chips are disposed on the first surface. The second IC chips are disposed on the second surface. The first read-only memory is connected with the first and the second IC chips disposed on the first region. The second read-only memory is connected with the first and the second IC chips disposed on the second region. 10 pins of the goldfinger connection interface are connected with the second read-only memory and the first and the second IC chips disposed on the second region to make them operate. At least 32 IC chips are effectively operated in single one memory.
Abstract: A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction.
Abstract: One or more memory systems, architectural structures, and/or methods of storing information in memory devices is disclosed to improve the data bandwidth and or to reduce the load on the communication links. The system may include one or more memory devices, one or more memory control circuits and one or more data buffer circuits. The memory system, architectural structure and/or method improves the ability of the communications links to transfer data downstream to the data buffer circuits. In one aspect, the memory control circuit receives a store command and a store data tag (Host tag) from a Host and sends the store data command and the store data tag to the data buffer circuits. No store data tag or control signal is sent over the communication links between the Host and the data buffer circuits, only data is sent over the communication links between the Host and the data buffer circuits.
November 29, 2017
Date of Patent:
August 27, 2019
International Business Machines Corporation
Steven R. Carlough, Susan M. Eickhoff, Warren E. Maule, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng
Abstract: According to an embodiment, a semiconductor memory device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells, a word line driving circuit, a sense amplifier circuit, and a controller. The memory cell connected to the selected word line is written with data using a write sequence including a plurality of write loops each including a write operation of applying a write voltage to the selected word line by the word line driving circuit and a verify operation of detecting data of the memory cell by the sense amplifier circuit. The controller determines an (n+k)-th (where n is an integer not less than 1 and k is an integer not less than 2) verify operation based on comparison between an n-th verify operation and an (n+1)-th verify operation in the write sequence.
Abstract: The present invention is directed to a magnetic memory device comprising a memory array structure that includes a first memory array comprising a first plurality of memory cells and a second memory array comprising a second plurality of memory cells. Each memory cell of the first and second plurality of magnetic memory cells includes a magnetic memory element and a two-terminal selector coupled in series. The memory array structure further includes a first multiplexer coupled to a third plurality of first conductive lines with each line connected to a respective column of the first plurality of memory cells; a second multiplexer coupled to a fourth plurality of first conductive lines with each line connected to a respective column of the second plurality of memory cells; a sense amplifier, whose input is connected to the output of the first multiplexer and the output of the second multiplexer; and one or more latches coupled to the sense amplifier.
Abstract: Sensing in non-volatile memory is performed using bias conditions that are dependent on the position of a selected memory cell within a group of non-volatile memory cells. During sensing, a selected memory cell receives a reference voltage while the remaining memory cells receive a read or verify pass voltage. For at least a subset of the unselected memory cells, the pass voltage that is applied is dependent upon the position of the selected memory cell in the group. As programming progresses from a memory cell at a first end of a NAND string toward a memory cell at a second end of the NAND string, for example, the pass voltage for at least a subset of the unselected memory cells that have already been subjected to programming may be increased. This technique may reduce the effects of an increased channel resistance that occurs as more memory cells are programmed.
Abstract: A storage system according to one aspect of the present invention includes a plurality of storage devices using flash memory as a storage medium. The flash memory used for the storage device may include flash memory configured to operate each cell as a cell capable of storing n-bit information or a cell capable of storing m-bit information (where n<m), where n=2 and m=3. The storage system may periodically acquire a number of remaining erasures from the storage device and predict the lifetime of the storage device by using the acquired number of remaining erasures and the storage device operation time. If the predicted lifetime is greater than a predetermined value (service life), a predetermined number of cells may be changed to cells capable of storing m-bit information.