Abstract: A memory system includes a memory device having a plurality of memory blocks for storing data, and a controller configured to perform an erase operation including plural unit erase operations to erase data stored in at least one target memory block included in the plurality of memory blocks. The controller can be configured to perform at least some of the plural unit erase operations onto the at least one target memory block before the at least one target memory block allocated for storing data.

Abstract: Embodiments herein relate to magnetically doping a spin orbit torque electrode (SOT) in a magnetic random access memory apparatus. In particular, the apparatus may include a free layer of a magnetic tunnel junction (MTJ) coupled to a SOT electrode that is magnetically doped to apply an effective magnetic field on the free layer, where the free layer has a magnetic polarization in a first direction and where current flowing through the magnetically doped SOT electrode is to cause the magnetic polarization of the free layer to change to a second direction that is substantially opposite to the first direction.

Abstract: A memory device includes a plurality of bit lines extending in a first direction, a plurality of lower memory cells below the bit lines and connected to the plurality of bit lines, and a plurality of upper memory cells above the plurality of bit lines and connected to the plurality of bit lines. The memory device comprises a plurality of cell array regions and a plurality of bit line contact regions alternately stacked in the first direction, the plurality of upper memory cells and the plurality of lower memory cells are located in the cell array regions, and only one of either the plurality of upper memory cells or the plurality of lower memory cells are arranged in at least one of the bit line contact regions.

Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented; and a level of memory control circuits, where the memory control circuits is disposed either above or below the plurality of memory cells.

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

Abstract: A vertical 3D memory device may comprise: a substrate including a plurality of conductive contacts each coupled with a respective one of a plurality of digit lines; a plurality of word line plates separated from one another with respective dielectric layers on the substrate, the plurality of word line plates including at least a first set of word lines separated from at least a second set of word lines with a dielectric material extending in a serpentine shape and at least a third set of word lines separated from at least a fourth set of word lines with a dielectric material extending in a serpentine shape; at least one separation layer separating the first set of word lines and the second set of word lines from the third set of word lines and the fourth set of word lines, wherein the at least one separation layer is parallel to both a digit line and a word line; and a plurality of storage elements each formed in a respective one of a plurality of recesses such that a respective storage element is surrounded

Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the channel is isolated from another channel disposed directly above the channel.

Abstract: The present disclosure provides a data search system and a data search method for determining whether there is stored information data matched with query information data in a storage circuit. The data search system comprises a storage circuit, a control circuit, and a feature extraction circuit, wherein the storage circuit comprises at least one storage unit which comprises a memristor crossbar array, a read/write unit, a decoder and a multiplexer, and the feature extraction circuit is configured to extract feature values of the query data. In the data search method, both the data matching process and the data storage process are performed in the memristor crossbar array under the control of the control circuit, which thus largely reduces the amount of data transmission while greatly improving the speed of data search using the characteristics of parallel calculation of the memristor crossbar array.

Abstract: A bistable device allows supercurrent to flow when functioning in one regime, wherein magnetization directions of different magnetic layers are antiparallel, but restricts supercurrent when switched to function in a resistive regime, wherein the magnetization directions are parallel. In the first regime, the device acts as a Josephson junction, which allows it to be used in superconducting quantum interference devices (SQUIDs) and other circuits in which quantization of magnetic flux in a superconducting loop is desired. In the second, resistive regime, flux quantization is effectively eliminated in loops containing the device, and current is diverted to parallel superconducting components. The bistable device thereby acts as a superconducting switch, useful for a variety of circuit applications, including to steer current for memory or logic circuits, adjust logical circuit functionality at runtime, or to burn off stray flux during cooldown.

Abstract: A memory device includes: first conductive lines extending in a first direction; second conductive lines extending in a second direction intersecting the first direction; a plurality of memory cells disposed at intersection portions of the first conductive lines and the second conductive lines; first selection transistors respectively connected to the first conductive lines, the first selection transistors constituting a plurality of groups; and first discharge circuits respectively connected to the plurality of groups of first selection transistors, each of the first discharge circuits discharging a group of first conductive lines corresponding thereto among the first conductive lines in response to a gate control signal.

Abstract: A memory device applies different refresh rates to target data (or objective data) according to data characteristics (i.e., required reliability levels). The memory device includes a memory cell array provided with a plurality of memory cells, a row decoder configured to selectively activate word lines of the memory cell array in response to a row address signal, and a refresh controller configured to output the row address signal in response to the row address signal. The refresh controller controls a refresh ratio of a first storage region and a second storage region contained in the memory cell array in response to a changeable refresh control value.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure having a dimension, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure has a dimension that is different from the dimension of the main cell structure, in which the main cell structure and the reference cell structure include a switching element arranged between a pair of conductors.

Abstract: A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction.

Abstract: This disclosure relates to a low-resistance monosilicide electrode and method of making the monosilicide electrode. A cell film stack is first formed on a substrate of a wafer. The top layer of this cell film stack is silicon. The cell film stack is then etched to form at least one pillar. Dielectric is deposited to fill the gaps between the pillars. The wafer is then planarized to expose the top silicon layer. The exposed top silicon layer is converted into a nickel monosilicide layer by way of a thermal solid-state reaction between nickel and the silicon layer. This nickel monosilicide layer forms the monosilicide electrode.

Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.

Abstract: An electron device using a crossbar array and capable of implementing a high-speed and high-reliability process is provided. An operational processing device (100) includes a crossbar array (110); a row selecting/driving circuit (120) electrically coupling to a row line; a column selecting/driving circuit (130) electrically coupling to a column line; and a control part (140) controlling each part. The control part (140) is capable of applying, from the row selecting/driving circuit (120), an output signal received by the row selecting/driving circuit (120) or applying, from the column selecting/driving circuit (130), an output signal received by the column selecting/driving circuit (130).

Abstract: In one embodiment, a computing system may write a first set of pixel values in a tile order into a first buffer with the pixel values organized into a first set of tiles. The system may generate first validity data for the first set of tiles. The first validity data may include a validity indicator for each tile to indicate if that tile is a valid tile. The system may read from the first buffer a first subset of pixel values in a pixel row order corresponding to pixel rows of the first set of tiles based on the valid data. The first subset of pixel values may be associated with valid tiles of the first set of tiles. The system may send the first subset of pixel values and the first validity data of the first set of tiles to a display via an output data bus.

Abstract: A resistance variable memory device may include a plurality of tiles in which memory cells are arranged. The first to third level of the word lines may be sequentially stacked on the plurality of tile regions with the decoding circuits along rows of the tile regions. A first level of the bit lines may be interposed between the first level of the word lines and the second level of the word lines. A first level of the bit lines may be extended along columns of the tile regions. The second level of the bit lines may be interposed between the second level of the word lines and the third level of the word lines. The second level of the bit lines may be extended along the columns of the tile regions. The first and third levels of the word lines at a selected row of a selected tile region among the tile regions and the second level of the bit lines at a selected column of the selected tile region may be controlled by a decoding circuit of the selected tile region.

Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.

Abstract: Methods, apparatuses, and systems related to a memory device are described. The memory device may include a sense amplifier that is configured to simultaneously precharge sensing nodes therein and compensate for threshold voltage mismatches between any transistors therein. The sense amplifier may be configured to charge gut nodes therein without connecting to a separate precharging voltage.