Patents Examined by Harry W Byrne
  • Patent number: 11158652
    Abstract: A 3D memory device, the device including: a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel; and a plurality of bit-line pillars, where each bit-line pillar of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the channel is isolated from another channel disposed directly above the channel.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: October 26, 2021
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Eli Lusky
  • Patent number: 11158673
    Abstract: A vertical 3D memory device may comprise: a substrate including a plurality of conductive contacts each coupled with a respective one of a plurality of digit lines; a plurality of word line plates separated from one another with respective dielectric layers on the substrate, the plurality of word line plates including at least a first set of word lines separated from at least a second set of word lines with a dielectric material extending in a serpentine shape and at least a third set of word lines separated from at least a fourth set of word lines with a dielectric material extending in a serpentine shape; at least one separation layer separating the first set of word lines and the second set of word lines from the third set of word lines and the fourth set of word lines, wherein the at least one separation layer is parallel to both a digit line and a word line; and a plurality of storage elements each formed in a respective one of a plurality of recesses such that a respective storage element is surrounded
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Fantini, Corrado Villa, Paolo Tessariol
  • Patent number: 11145361
    Abstract: A bistable device allows supercurrent to flow when functioning in one regime, wherein magnetization directions of different magnetic layers are antiparallel, but restricts supercurrent when switched to function in a resistive regime, wherein the magnetization directions are parallel. In the first regime, the device acts as a Josephson junction, which allows it to be used in superconducting quantum interference devices (SQUIDs) and other circuits in which quantization of magnetic flux in a superconducting loop is desired. In the second, resistive regime, flux quantization is effectively eliminated in loops containing the device, and current is diverted to parallel superconducting components. The bistable device thereby acts as a superconducting switch, useful for a variety of circuit applications, including to steer current for memory or logic circuits, adjust logical circuit functionality at runtime, or to burn off stray flux during cooldown.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: October 12, 2021
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Eric C. Gingrich, Randall M. Burnett, Donald L. Miller
  • Patent number: 11145365
    Abstract: The present disclosure provides a data search system and a data search method for determining whether there is stored information data matched with query information data in a storage circuit. The data search system comprises a storage circuit, a control circuit, and a feature extraction circuit, wherein the storage circuit comprises at least one storage unit which comprises a memristor crossbar array, a read/write unit, a decoder and a multiplexer, and the feature extraction circuit is configured to extract feature values of the query data. In the data search method, both the data matching process and the data storage process are performed in the memristor crossbar array under the control of the control circuit, which thus largely reduces the amount of data transmission while greatly improving the speed of data search using the characteristics of parallel calculation of the memristor crossbar array.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: October 12, 2021
    Assignee: PEKING UNIVERSITY
    Inventors: Jinfeng Kang, Peng Huang, Xiaoyan Liu, Lifeng Liu
  • Patent number: 11145363
    Abstract: A memory device includes: first conductive lines extending in a first direction; second conductive lines extending in a second direction intersecting the first direction; a plurality of memory cells disposed at intersection portions of the first conductive lines and the second conductive lines; first selection transistors respectively connected to the first conductive lines, the first selection transistors constituting a plurality of groups; and first discharge circuits respectively connected to the plurality of groups of first selection transistors, each of the first discharge circuits discharging a group of first conductive lines corresponding thereto among the first conductive lines in response to a gate control signal.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Hyung Dong Lee
  • Patent number: 11133050
    Abstract: A memory device applies different refresh rates to target data (or objective data) according to data characteristics (i.e., required reliability levels). The memory device includes a memory cell array provided with a plurality of memory cells, a row decoder configured to selectively activate word lines of the memory cell array in response to a row address signal, and a refresh controller configured to output the row address signal in response to the row address signal. The refresh controller controls a refresh ratio of a first storage region and a second storage region contained in the memory cell array in response to a changeable refresh control value.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: September 28, 2021
    Assignee: SK hynix Inc.
    Inventor: Ho Sung Cho
  • Patent number: 11127461
    Abstract: A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: September 21, 2021
    Assignee: SUNRISE MEMORY CORPORATION
    Inventor: Eli Harari
  • Patent number: 11127459
    Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices incorporating reference cells for achieving high sensing yield. The present disclosure provides a memory device including a main cell structure having a dimension, and a reference cell structure electrically coupled to the main cell structure. The reference cell structure has a dimension that is different from the dimension of the main cell structure, in which the main cell structure and the reference cell structure include a switching element arranged between a pair of conductors.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: September 21, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Curtis Chun-I Hsieh, Wei-Hui Hsu, Wanbing Yi, Yi Jiang, Kai Kang, Juan Boon Tan
  • Patent number: 11114139
    Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: September 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Sung Shin, Ik-Joon Choi, So-Young Kim, Tae-Kyu Byun, Jae-Youn Youn
  • Patent number: 11114157
    Abstract: This disclosure relates to a low-resistance monosilicide electrode and method of making the monosilicide electrode. A cell film stack is first formed on a substrate of a wafer. The top layer of this cell film stack is silicon. The cell film stack is then etched to form at least one pillar. Dielectric is deposited to fill the gaps between the pillars. The wafer is then planarized to expose the top silicon layer. The exposed top silicon layer is converted into a nickel monosilicide layer by way of a thermal solid-state reaction between nickel and the silicon layer. This nickel monosilicide layer forms the monosilicide electrode.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: September 7, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventor: Takuya Futase
  • Patent number: 11100992
    Abstract: In one embodiment, a computing system may write a first set of pixel values in a tile order into a first buffer with the pixel values organized into a first set of tiles. The system may generate first validity data for the first set of tiles. The first validity data may include a validity indicator for each tile to indicate if that tile is a valid tile. The system may read from the first buffer a first subset of pixel values in a pixel row order corresponding to pixel rows of the first set of tiles based on the valid data. The first subset of pixel values may be associated with valid tiles of the first set of tiles. The system may send the first subset of pixel values and the first validity data of the first set of tiles to a display via an output data bus.
    Type: Grant
    Filed: February 2, 2021
    Date of Patent: August 24, 2021
    Assignee: Facebook Technologies, LLC
    Inventor: Larry Seiler
  • Patent number: 11100983
    Abstract: An electron device using a crossbar array and capable of implementing a high-speed and high-reliability process is provided. An operational processing device (100) includes a crossbar array (110); a row selecting/driving circuit (120) electrically coupling to a row line; a column selecting/driving circuit (130) electrically coupling to a column line; and a control part (140) controlling each part. The control part (140) is capable of applying, from the row selecting/driving circuit (120), an output signal received by the row selecting/driving circuit (120) or applying, from the column selecting/driving circuit (130), an output signal received by the column selecting/driving circuit (130).
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: August 24, 2021
    Assignee: Winbond Electronics Corp.
    Inventor: Masaru Yano
  • Patent number: 11094378
    Abstract: A resistance variable memory device may include a plurality of tiles in which memory cells are arranged. The first to third level of the word lines may be sequentially stacked on the plurality of tile regions with the decoding circuits along rows of the tile regions. A first level of the bit lines may be interposed between the first level of the word lines and the second level of the word lines. A first level of the bit lines may be extended along columns of the tile regions. The second level of the bit lines may be interposed between the second level of the word lines and the third level of the word lines. The second level of the bit lines may be extended along the columns of the tile regions. The first and third levels of the word lines at a selected row of a selected tile region among the tile regions and the second level of the bit lines at a selected column of the selected tile region may be controlled by a decoding circuit of the selected tile region.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: August 17, 2021
    Assignee: SK hynix Inc.
    Inventor: Dong Keun Kim
  • Patent number: 11087208
    Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 10, 2021
    Assignee: University of Dayton
    Inventors: Chris Yakopcic, Tarek M. Taha, Md Raqibul Hasan
  • Patent number: 11087805
    Abstract: Methods, apparatuses, and systems related to a memory device are described. The memory device may include a sense amplifier that is configured to simultaneously precharge sensing nodes therein and compensate for threshold voltage mismatches between any transistors therein. The sense amplifier may be configured to charge gut nodes therein without connecting to a separate precharging voltage.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Kyuseok Lee
  • Patent number: 11081197
    Abstract: A methodology and structure for performing an erase verify in non-volatile memory is described. Both the odd wordlines and the even wordlines are driven to a high voltage level. This can be done simultaneously. The simultaneous charging of both the odd wordlines and the even wordlines, even when the erase verify will occur on only one of the odd or even wordlines reduces RC delay in the charging of the wordlines. After the odd and even wordlines are charged, then one set of wordlines, either the odd or even wordlines, is dropped to the erase verify voltage. The erase sense operation is then performed.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: August 3, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Xiang Yang, Yu-Chung Lien
  • Patent number: 11074958
    Abstract: A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: July 27, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xing Hu, Chuanzeng Liang, Shihai Xiao, Kanwen Wang
  • Patent number: 11074967
    Abstract: A memory is provided that includes a current mirror that controls the amount of current conducted by a head-switch transistor for a memory power supply rail during a core-power-lowering write assist period.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: July 27, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Adithya Bhaskaran, Mukund Narasimhan, Shiba Narayan Mohanty
  • Patent number: 11069406
    Abstract: A nonvolatile memory device includes a differential current driver that receives a first differential signal and a second differential signal, which are based on a temperature, and generates a first compensation current and a second compensation current corresponding to a difference value between the first and second differential signals. A current mirror circuit copies a first current, which is a sum of a reference current and the first compensation current, to generate a second current having a same value as a value of the first current and regulates the reference current depending on a difference value of the second current and the second compensation current. A trimming circuit generates a program current or a read current based on the regulated reference current.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Hoon Lim, Bilal Ahmad Janjua
  • Patent number: 11069697
    Abstract: A 3D memory device, the device including: a plurality of memory cells, where each of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain and a channel; a plurality of bit-line pillars, where each of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the channel includes a circular shape or an ellipsoidal shape.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: July 20, 2021
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han, Eli Lusky