Patents Examined by Harry W Byrne
  • Patent number: 10777237
    Abstract: There may be provided an electronic device, and more particularly, a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory cell array including a plurality of memory cells. The semiconductor memory device may include an operation control signal generator configured to receive a request for performing a target operation from the controller configured to control the semiconductor memory device and to generate a synchronizing signal for performing the target operation. The semiconductor memory device may include a temperature detect circuit configured to detect temperatures of the plurality of memory cells in response to the synchronizing signal.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: September 15, 2020
    Assignee: SK hynix Inc.
    Inventor: Byoung In Joo
  • Patent number: 10778414
    Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Peter John McElheny, Aravind Dasu
  • Patent number: 10770116
    Abstract: A memory device includes active circuitry configured to process a segment set that corresponds to a source data, wherein: the source data comprises information corresponding to a device operation, the source data having a block length representing a number of bits therein, and the segment set includes at least a first segment and a second segment, the first segment and the second segment each including number of bits less than the block length; and a set of die pads coupled to the active circuitry and configured to communicate the segment set for operating a second device, wherein the set includes a number of die pads less than the block length.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: September 8, 2020
    Assignee: Micron Technology
    Inventors: Vijayakrishna J. Vankayala, Liang Chen
  • Patent number: 10761754
    Abstract: Data can be received at a memory sub-system. A characteristic of the memory sub-system can be identified. A read voltage level can be determined based on the characteristic of the memory sub-system. A read operation can be performed at the memory sub-system based on the read voltage level to retrieve stored data. The received data can be stored at the memory sub-system based on the stored data that was retrieved from the read operation that is based on the read voltage level.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Zhenlei E. Shen, Zhengang Chen, Tingjun Xie, Jiangli Zhu
  • Patent number: 10755789
    Abstract: The invention provides a write protection circuit, which is applied to a data storage device. The data storage device comprises a controller and a plurality of flash memories. The flash memories comprise a write protection pin. The write protection circuit comprises a fuse and a switch. When the switch is operated in a turned on state, the fuse is directly grounded via the switch and therefore is burned, and a signal on the write protection pin of the flash memories becomes a signal with a low-level state so that the flash memories of the data storage device will be permanently inhibited to be written.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: August 25, 2020
    Assignee: Innodisk Corporation
    Inventor: Chih-Chieh Kao
  • Patent number: 10754584
    Abstract: The present invention provides a data processing method and system for a 2R1W memory. The data processing method comprises: selecting 2n+1 SRAM2P memories with the same depth and width in accordance with a depth and a width of the 2R1W memory to construct a hardware architecture of the 2R1W memory, one of the plurality of SRAM2P memories being an auxiliary memory, and the rest of the SRAM2P memories being main memories; and when the data are written in and/or read from the 2R1W memory, associating data in the main memories and data in the auxiliary memory in accordance with a current pointer address of the data and performing an XOR operation on the associated data to complete data writing and reading. Only extra ┬Żn of the memory area is required to construct the 2R1W memory based on a conventional SRAM unit.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: August 25, 2020
    Assignee: CENTEC NETWORKS (SU ZHOU) CO., LTD.
    Inventor: Jun Xu
  • Patent number: 10755774
    Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 25, 2020
    Assignee: Arm Limited
    Inventors: Vivek Nautiyal, Lalit Gupta, Fakhruddin Ali Bohra, Shri Sagar Dwivedi
  • Patent number: 10755194
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for constructing and programming quantum hardware for quantum annealing processes.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: August 25, 2020
    Assignee: Google LLC
    Inventors: Masoud Mohseni, Hartmut Neven
  • Patent number: 10748632
    Abstract: A nonvolatile memory device includes multiple memory cells including first memory cells and second memory cells. A method of programming the nonvolatile memory device includes: performing first programming to apply a programming forcing voltage to a bit line of each of the first memory cells; and dividing the second memory cells into a first cell group, a second cell group, and a third cell group, based on a threshold voltage of the second memory cells after performing the first programming. The method also includes performing second programming to apply a programming inhibition voltage to the bit line of each of the first memory cells and a bit line of each of memory cells of the first cell group. A level of the programming forcing voltage is lower than that of the programming inhibition voltage.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: August 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Won Yun, Hye-Jin Yim
  • Patent number: 10748586
    Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Kang-Yong Kim
  • Patent number: 10746835
    Abstract: Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2 F2.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Zengtao T. Liu
  • Patent number: 10748965
    Abstract: A semiconductor device includes a plurality of first conductive lines in a first wiring layer, a plurality of second conductive lines in a second wiring layer, and a plurality of memory cells between the first and second conductive lines in a first direction in a first region. A plurality of third conductive lines in the first wiring layer, a plurality of fourth conductive lines in the second wiring, and a plurality of first memory lines are in a second region. The third conductive lines extends in a second direction and are spaced from each other in a third direction. The fourth conductive lines extend in the second direction and are spaced in the third direction. The first memory lines are between the third conductive lines and the fourth conductive lines in the first direction. The first memory lines comprise the same materials as the memory cells.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: August 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Takayuki Miyazaki
  • Patent number: 10741261
    Abstract: In one embodiment there is a method for calculating a timer at a storage device including a plurality of memory portions for storing data and a memory controller for performing operations on the memory portions, the method comprises receiving a request to perform an initial operation on a memory portion; determining an operational characteristic associated with the initial operation to be performed on the memory portion; and calculating an amount of time for a memory portion timer based on the operational characteristics before the initiation of the initial operation on the memory portion, wherein performance of a subsequent operation for another memory portion is delayed until the amount of time for the memory portion timer has elapsed since initiation of the operation on the memory portion.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: August 11, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sahil Sharma, Phil Reusswig, Rohit Sehgal, Niles Yang
  • Patent number: 10734577
    Abstract: A memory device including a template layer is disclosed. The memory device also includes a memory layer connected to the template layer, where the memory layer has a variable resistance, and where the crystalline structure of the memory layer matches the crystalline structure of the template layer. The memory device also includes a conductive top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 4, 2020
    Assignee: 4DS MEMORY, LIMITED
    Inventor: Seshubabu Desu
  • Patent number: 10734048
    Abstract: One or more control lines other than those used to activate a non-volatile memory cell may be used to sense a data value of the cell. For example, an apparatus may include a selection circuit that selects, based on an address corresponding to a non-volatile memory cell included an array of non-volatile memory cells, a word line coupled to the non-volatile memory cells to activate the non-volatile memory cell. An amplifier circuit may sense a data value stored in the non-volatile memory cell based on a sense signal having a voltage level based on voltage levels of one or more other word lines of the array of non-volatile memory cells. In another example, a data value of a non-volatile memory cell coupled to a word line may be sensed based on the voltage levels of one or more dummy sense lines within the array.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: August 4, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yadhu Vamshi Vancha, James Hart, Jeffrey Koon Yee Lee, Tz-Yi Liu, Ali Al-Shamma, Yingchang Chen
  • Patent number: 10734056
    Abstract: In a particular implementation, an apparatus including first and second bias circuits and an inner amplifier provides sense amplifier offset cancellation. The inner amplifier includes: first and second current generators configured to replicate respective first and second currents from the first and second bias circuits, first and second transistors configured to transform the first and second currents into voltage samples, and first and second capacitors configured to store the voltage samples. In a sampling phase, a sampling of the first and second currents may be performed in the inner amplifier, and further, in an amplification phase, an amplification of the stored voltage samples may also be performed in the inner amplifier.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: August 4, 2020
    Assignee: Arm Limited
    Inventors: El Mehdi Boujamaa, Cyrille Nicolas Dray
  • Patent number: 10726913
    Abstract: Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: July 28, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideki Uochi, Koichiro Kamata
  • Patent number: 10726920
    Abstract: Techniques are provided for pre-charging NAND strings during a programming operation. The NAND strings are in a block that is divided into vertical sub-blocks. During a pre-charge phase of a programming operation, an overdrive voltage is applied to some memory cells and a bypass voltage is applied to other memory cells. The overdrive voltage allows the channel of an unselected NAND string to adequately charge during the pre-charge phase. Adequate charging of the channel helps the channel voltage to boost to a sufficient level to inhibit programming of an unselected memory cell during a program phase. Thus, program disturb is prevented, or at least reduced. The technique allows, for example, programming of memory cells in a middle vertical sub-block without causing program disturb of memory cells that are not to receive programming.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: July 28, 2020
    Assignee: SanDisk Technologies LLC
    Inventor: Xiang Yang
  • Patent number: 10726937
    Abstract: A semiconductor device includes: a non-volatile memory including a normal region, a self-repair region and a redundancy region, each having a plurality of cells; a first boot-up control block suitable for controlling a first boot-up operation to detect defective cells of the normal region and store a defective address in a first latch unit; a self-program control block suitable for controlling a self-program operation to program the defective address stored in the first latch unit into the self-repair region; and a second boot-up control block suitable for controlling a second boot-up operation to read out data of the normal region based on an input address while reading out data of the redundancy region instead of the data of the normal region when data of the self-repair region coincides with the input address.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventor: Young-Bo Shim
  • Patent number: 10720448
    Abstract: A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: July 21, 2020
    Assignee: SUNRISE MEMORY CORPORATION
    Inventor: Eli Harari