Abstract: The present disclosure discloses a memory access interface device. The clock generation circuit thereof generates reference clocks. Each of the DDR access signal transmission circuits thereof, under a DDR mode, adjusts a phase and a duty cycle of one of DDR access signals according to one of DDR reference clock signals to generate one of output access signals to access the memory device. The data signal transmission circuit thereof, under an SDR mode, applies a minimum latency on an SDR data signal according to the command and address reference clock signal to generate an output SDR data signal to access the memory device. The command and address signal transmission circuit thereof, under either the DDR or SDR mode, applies a programmable latency on a command and address signal according to the command and address reference clock signal to generate an output command and address signal to access the memory device.

Abstract: A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0° to about 90° relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes first memory cells coupled to control circuit and a particular word line and storing a first cell data. The apparatus also includes second memory cells coupled to a source side neighbor word line disposed on a source side of the particular word line and storing second cell threshold voltages programmed after the first cell data. The control circuit senses the second cell threshold voltages at a first time while applying a predetermined initial read voltage to the source side neighbor word line. The control circuit senses the first cell data at a second time while iteratively applying one of a plurality of particular read voltages to the particular word line and simultaneously and iteratively applying one of a plurality of neighbor pass voltages to the source side neighbor word line based on the second cell threshold voltages.

Abstract: Methods and apparatuses for erasing data on a plurality of ferroelectric memory cells in a memory cell array in a memory apparatus are disclosed. An example apparatus includes: a memory cell array including a first plurality of word lines; a digit line; and a plurality of ferroelectric memory cells; a control circuit that provides a section select signal and a word line select signal to select a second plurality of word lines among the first plurality of word lines responsive to an address; and an address decoder that activates the second plurality of word lines. Each ferroelectric memory cell includes: a ferroelectric capacitor having a first terminal coupled to a cell plate node and a second terminal coupled to a selection circuit that couples the digit line to the second terminal responsive to a signal on a corresponding word line of the second plurality of word lines.

Abstract: Signal edge sharpener circuitry is operably connected to the word lines in a memory array to pull up a rising edge of a signal on the word line and/or to pull down a falling edge of the signal on the word line. Pulling the signal up and/or down reduces the amount of time the word line is asserted and reduces the amount of time between precharge operations.

Abstract: A voltage controlled magnetic random memory unit, a memory, and a logic device thereof. The memory unit includes: a ferroelectric layer applied with a first positive or negative voltage to control a directional switching of magnetization; a spin-orbit coupling layer located above the ferroelectric layer and applied with a second voltage to produce a spin current in a direction perpendicular to the spin-orbit coupling layer; a first magnetic layer located above the spin-orbit coupling layer, wherein, the spin current induces a random up and down magnetic switching of the first magnetic layer. The spin current may induce a directional switching of the first magnetic layer in conjunction with the first voltage applied to the ferroelectric layer.

Abstract: An aspect a bit selection path configured to propagate a bit selection signal. The bit selection path includes bit selection delay circuitry defining a bit selection delay. The memory array includes a row selection path configured to propagate a row selection signal. The row selection path includes row selection delay circuitry defining a row selection delay. The memory array includes local selection circuitry. The local selection circuitry is configured to receive the bit selection signal from the bit selection path before the row selection signal from the row selection path according to the bit selection delay and the row selection delay.

Abstract: According to one implementation of the present disclosure, an integrated circuit includes first and second word-line decoder circuitry, two or more memory instances coupled to the first and second word-line decoder circuitry; and a control block circuitry coupled to the first and second word-line decoder circuitry and the two or more memory instances. Also, a pin bus enabled in the control block circuitry may be configured to at least partially control selection of one or more of the two or more memory instances.

Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.

Abstract: Systems and methods of modeling the structure and behavior of the quantum continuum based on geometrical principles are provided. In some embodiments, systems and methods of modeling quantum structure and behavior may include modeling a region of space as a three-dimensional projection of a field of N-dimensional hard-spheres, modeling a stable particle within the region of space as a locally stably packed set of hard-spheres, defining an energy subspace comprising one or more additional dimensions, and modeling an energy of the stable particle as an amount of hard-sphere geometry shifted out of the three spatial dimensions into the energy subspace sufficient for the set of hard-spheres to pack stably. Systems and methods for modeling virtual particles and performing quantum communication are also described.

Abstract: A method includes generating a bias signal from a first device, and applying the bias signal to a second device, the first device having (a) a superconducting trace and (b) a superconducting quantum interference device (SQUID), in which a first terminal of the SQUID is electrically coupled to a first end of the superconducting trace, and a second terminal of the SQUID is electrically coupled to a second end of the superconducting trace, where generating the bias signal from the first device includes: applying a first signal ?1 to a first sub-loop of the SQUID; and applying a second signal ?2 to a second sub-loop of the SQUID, in which the first signal ?1 and the second signal ?2 are applied such that a value of a superconducting phase of the first device is incremented or decremented by a non-zero integer multiple n of 2?.

Abstract: A semiconductor storage device comprises first and second memory cells each including a variable-resistance element, a write driver, and a control circuit that concurrently performs an operation to read first data in the first memory cell and second data in the second memory cell, the operation to read the first data including a first write operation for a first time length and the operation to read the second data including a second write operation for a second time length. In the first write operation, the write driver applies, to the first memory cell, a first voltage for a third time length and a second voltage different from the first voltage for a fourth time length. In the second write operation, the write driver applies the first voltage to the second memory cell for a fifth time length longer than the third time length and longer than the fourth time length.

Abstract: In some aspects, a heterogeneous computing system includes a quantum processor unit and a classical processor unit. In some instances, variables defined by a computer program are stored in a classical memory in the heterogeneous computing system. The computer program is executed in the heterogeneous computing system by operation of the quantum processor unit and the classical processor unit. Instructions are generated for the quantum processor by a host processor unit based on values of the variables stored in the classical memory. The instructions are configured to cause the quantum processor unit to perform a data processing task defined by the computer program. The values of the variables are updated in the classical memory based on output values generated by the quantum processor unit. The classical processor unit processes the updated values of the variables.

Abstract: In one embodiment, a computing system may write a first set of pixel values in a tile order into a first buffer with the pixel values organized into a first set of tiles. The system may generate first validity data for the first set of tiles. The first validity data may include a validity indicator for each tile to indicate if that tile is a valid tile. The system may read from the first buffer a first subset of pixel values in a pixel row order corresponding to pixel rows of the first set of tiles based on the valid data. The first subset of pixel values may be associated with valid tiles of the first set of tiles. The system may send the first subset of pixel values and the first validity data of the first set of tiles to a display via an output data bus.

Abstract: A semiconductor device includes an information signal generation circuit configured to store the register information depending on an input control signal generated based on the mode register read command, and output the stored register information depending on an output control signal generated based on the mode register read command.

Abstract: A resistive memory device including a substrate, an isolation structure, a word line, a source line, a bit line and a resistive memory is provided. The substrate includes a body region, and first, second and third doped regions, the first and second doped regions are spaced apart from each other by the body region. The isolation structure is disposed in the substrate, and the second doped region and the third doped region are spaced apart from each other by the isolation structure. The word line is disposed on the substrate, the first and second doped regions are located at opposite sides of the word line, and the first and third doped regions are located at the opposite sides of the word line. The source line is disposed on the substrate and electrically connected with the first doped region. The bit line and the resistive memory are disposed on the substrate, and the third doped region is electrically connected with the bit line via the resistive memory.

Abstract: Methods, devices, and systems are provided for identifying dropouts in analyte monitoring system sensor data including segmenting sensor data into a plurality of time series wherein each time series is associated with a different instance of a repeating event, selecting a first time series to analyze for dropouts from the plurality of time series; comparing the selected first time series to a second time series among the plurality of time series, determining whether the selected first time series includes a portion that is more than a predefined threshold lower than a corresponding portion of the second time series, and displaying, on a computer system display, an indication that the selected first time series includes a dropout if the selected first time series includes a portion that is more than the predefined threshold lower than the corresponding portion of the second time series.

Abstract: A two-stage gated-diode sense amplifier includes a first transistor connected to an input node, a second transistor connected to a boost node, the input node and a setting line, a first inverter including a third transistor connected to a power supply voltage (VDD), a first output corresponding to the first inverter and the setting line, and a fourth transistor connected to ground, the first output and the setting line, a fifth transistor connected to the first output, the first transistor and the boost node, and a second associated with a second output corresponding to the second inverter, the second inverter including a sixth transistor connected to VDD, the second output and the first output, and a seventh transistor connected to ground, the second output and the first output.

Abstract: A stacked memory device includes: a logic semiconductor die; a plurality of memory semiconductor dies stacked with the logic semiconductor die, wherein each of the memory semiconductor dies includes a memory integrated circuit and one or more of the memory semiconductor dies is a calculation semiconductor die including a calculation unit; and through-silicon vias electrically connecting the logic semiconductor die and the plurality of memory semiconductor dies, wherein each of the calculation units is configured to perform calculations based on broadcast data and internal data and to generate calculation result data, wherein the broadcast data is commonly provided to the calculation semiconductor dies through the through-silicon vias, and the internal data is respectively read from the memory integrated circuits of the calculation semiconductor dies.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for constructing and programming quantum hardware for quantum annealing processes.