Abstract: A methodology and structure for performing an erase verify in non-volatile memory is described. Both the odd wordlines and the even wordlines are driven to a high voltage level. This can be done simultaneously. The simultaneous charging of both the odd wordlines and the even wordlines, even when the erase verify will occur on only one of the odd or even wordlines reduces RC delay in the charging of the wordlines. After the odd and even wordlines are charged, then one set of wordlines, either the odd or even wordlines, is dropped to the erase verify voltage. The erase sense operation is then performed.

Abstract: A memory is provided that includes a current mirror that controls the amount of current conducted by a head-switch transistor for a memory power supply rail during a core-power-lowering write assist period.

Abstract: A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.

Abstract: A nonvolatile memory device includes a differential current driver that receives a first differential signal and a second differential signal, which are based on a temperature, and generates a first compensation current and a second compensation current corresponding to a difference value between the first and second differential signals. A current mirror circuit copies a first current, which is a sum of a reference current and the first compensation current, to generate a second current having a same value as a value of the first current and regulates the reference current depending on a difference value of the second current and the second compensation current. A trimming circuit generates a program current or a read current based on the regulated reference current.

Abstract: A 3D memory device, the device including: a plurality of memory cells, where each of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain and a channel; a plurality of bit-line pillars, where each of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where the bit-line pillars are vertically oriented, where the channel is horizontally oriented, and where the channel includes a circular shape or an ellipsoidal shape.

Abstract: Embodiments of 3D memory devices and methods for operating the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes a plurality of memory decks each including a plurality of memory layers in a vertical direction, and a plurality of first dummy memory layers between the first and second memory decks in the vertical direction. Each memory layer in a first memory deck of the plurality of memory decks is first programmed. The first programming includes applying a program voltage to the memory layer and a channel pass voltage smaller than the program voltage to each of the rest of the memory layers in the first memory deck. Each memory layer in a second memory deck of the plurality of memory decks above the first memory deck is second programmed. The second programming includes applying the program voltage to the memory layer and the channel pass voltage to each of the rest of the memory layers in the second memory deck.

Abstract: A resistance variable memory device may include a plurality of tiles in which memory cells are arranged. The first to third level of the word lines may be sequentially stacked on the plurality of tile regions with the decoding circuits along rows of the tile regions. A first level of the bit lines may be interposed between the first level of the word lines and the second level of the word lines. A first level of the bit lines may be extended along columns of the tile regions. The second level of the bit lines may be interposed between the second level of the word lines and the third level of the word lines. The second level of the bit lines may be extended along the columns of the tile regions. The first and third levels of the word lines at a selected row of a selected tile region among the tile regions and the second level of the bit lines at a selected column of the selected tile region may be controlled by a decoding circuit of the selected tile region.

Abstract: A hybrid computer generates samples for machine learning. The hybrid computer includes a processor that implements a Boltzmann machine, e.g., a quantum Boltzmann machine, which returns equilibrium samples from eigenstates of a quantum Hamiltonian. Subsets of samples are provided to training and validations modules. Operation can include: receiving a training set; preparing a model described by an Ising Hamiltonian; initializing model parameters; segmenting the training set into subsets; creating a sample set by repeatedly drawing samples until the determined number of samples has been drawn; and updating the model. Operation can include partitioning the training set into input and output data sets, and determining a conditional probability distribution that describes a probability of observing an output vector given a selected input vector, e.g.

Abstract: A SRAM array is provided. The SRAM array includes a first bit cell array and a second bit cell array arranged along a first direction, and a strap cell arranged along a second direction and positioned between the first bit cell array and the second bit cell array along the first direction. The strap cell includes a first P-type well region, two first N-type well regions, a second N-type well region. The two first N-type well regions are separated by the first P-type well region in the first direction, and the second N-type well region and one of the two first N-type well regions are separated by the first P-type well region in the second direction. The strap cell further includes a deep N-type well region underlying the two first N-type well regions and the second N-type well region.

Abstract: In a particular implementation, an apparatus including first and second bias circuits and an inner amplifier provides sense amplifier offset cancellation. The inner amplifier includes: first and second current generators configured to replicate respective first and second currents from the first and second bias circuits, first and second transistors configured to transform the first and second currents into voltage samples, and first and second capacitors configured to store the voltage samples. In a sampling phase, a sampling of the first and second currents may be performed in the inner amplifier, and further, in an amplification phase, an amplification of the stored voltage samples may also be performed in the inner amplifier.

Abstract: A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

Abstract: An electronic device includes a semiconductor memory comprising column lines, row lines crossing the column lines, memory cells located at intersections between the column lines and the row lines, dummy insulating patterns located adjacent to the memory cells, liner layers formed on sidewalls of the memory cells, and dummy liner layers formed on sidewalls of the dummy insulating patterns.

Abstract: A memory system includes a semiconductor memory device including a memory block; and a scrambler and ECC block configured to generate program data using data received from a host, generate one or more data sets using the program data and page information data, and output the one or more data sets, during a write operation; and a memory controller configured to output the one or more data sets to the semiconductor memory device and to control the semiconductor memory device, wherein the semiconductor memory device is configured to read the page information data stored in each of the plurality of pages and detect, from among the plurality of pages, an erased page or a program-interrupted page in which a sudden power-off (SPO) has occurred during a boot operation.

Abstract: An electronic storage memory device is disclosed. The memory device includes a first conductive layer, and also includes a memory layer connected to the first conductive layer, where the memory layer has a variable resistance, and where no amorphous layer exists between the first conductive layer and the memory layer.

Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.

Abstract: Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.

Abstract: A 3D memory device, the device including: a plurality of memory cells, where each of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source and a drain; a plurality of bit-line pillars, where each of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where each of the plurality of bit-line pillars includes metal atoms such that the plurality of bit-line pillars have at least partial metallic properties; and a thermal path from the bit-line pillars to an external surface of the device to remove heat. Various 3D processing flows and methods are also disclosed.

Abstract: A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.

Abstract: Provided herein are memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal.