Abstract: A semiconductor apparatus includes a decoder configured to decode an internal command, and generate a first decoding command and a second decoding command. The semiconductor apparatus may include an output timing control circuit configured to delay the second decoding command by a predetermined cycle of the internal clock, and output a delayed decoding command. The semiconductor apparatus may include an input/output control latch circuit configured to output the internal address as a first latch address based on the second decoding command and the delayed decoding command. The semiconductor apparatus may include an input control latch circuit configured to output the internal address as a second latch address based on the first decoding command.

Abstract: A nonvolatile memory device includes a nonvolatile memory cell, a sensing circuit coupled between a sensing input line coupled to a bit line of the nonvolatile memory cell and a sensing output line, a sensing output grounding portion fixing an output signal of the sensing circuit at a low level if the output signal of the sensing circuit has a low level, and a bit line grounding portion fixing a bit line voltage at a ground voltage if the output signal of the sensing circuit is fixed at a low level.

Abstract: A memory structure, includes active columns of polysilicon formed above a semiconductor substrate, each active column includes one or more vertical NOR strings, with each NOR string having thin-film storage transistors sharing a local source line and a local bit line, the local bit line is connected by one segment of a segmented global bit line to a sense amplifier provided in the semiconductor substrate.

Abstract: Embodiments of systems and methods for management and/or optimization of non-volatile memory read thresholds using improved time and temperature tagging are described. In some embodiments, time and temperature tagging can be optimized based on time that it takes to perform read threshold calibration, the expected change in temperature, and/or the impact of this change on bit error rate. In some embodiments, a model of an environmental parameter can be determined and associated read thresholds can be pre-calculated. If the measured environmental parameter is within a threshold of the model for the environmental parameter, a pre-calculated read threshold value can be used instead of performing read threshold calibration. Advantageously, power consumption can be reduced and throughput for the memory device can be increased.

Abstract: A non-volatile semiconductor storage device including a first potential retention line configured to retain a potential corresponding to data read from the memory cell, a second potential retention line configured to retain a reference potential read from the memory cell in which the reference potential is written after the data is read out, a sense amplifier configured to amplify a difference between the potential retained by the first potential retention line and the reference potential for reading out the data from the memory cell, a first offset adjustment circuit connected to the first potential retention line, for adjusting an offset for the potential, a second offset adjustment circuit connected to the second potential retention line, and an offset command signal supply circuit configured to supply a first offset command signal to the first offset adjustment circuit so as to control the offset.

Abstract: A memory device includes a first die configured to: generate a segment set based on a source data, wherein: the source data is information corresponding to a device operation, the source data having a block length representing a number of bits therein, the segment set including at least a first segment and a second segment, the first segment and the second segment having a number of bits less than the block length, and communicate the segment set with the second die; a second die configured to process the segment set according to the device operation; and a set of inter-die connectors electrically coupling the first die and the second die, the inter-die connectors include a number of dedicated Through-Silicon-Vias (TSVs), wherein the number is less than the block length.

Abstract: A semiconductor memory device includes a cell string and a peripheral circuit. The cell string includes a plurality of memory cells coupled between a common source line and a bit line. The peripheral circuit controls a voltage supplied to the cell string to program a selected memory cell of the cell string by performing a program loop including a program section, a detrap section, and a verify section. Also, the peripheral circuit is configured to supply a program voltage to a word line coupled to the selected memory cell among the plurality of memory cells during the program section. The peripheral circuit further supplies a detrap voltage to the cell string during the detrap section and supplies a verify voltage to the word line during the verify section.

Abstract: There is disclosed a memory element including a memory layer that has a magnetization perpendicular to a film face; a magnetization-fixed layer that has a magnetization that is perpendicular to the film face; and an insulating layer that is provided between the memory layer and the magnetization-fixed layer, wherein an electron that is spin-polarized is injected in a lamination direction of a layered structure, and thereby the magnetization direction of the memory layer varies and a recording of information is performed, a magnitude of an effective diamagnetic field which the memory layer receives is smaller than a saturated magnetization amount of the memory layer, and in regard to the insulating layer and the other side layer with which the memory layer comes into contact at a side opposite to the insulating layer, at least an interface that comes into contact with the memory layer is formed of an oxide film.

Abstract: Dynamic redundancy buffers for use with a device are disclosed. The dynamic redundancy buffers allow a memory array of the device to be operated with high write error rate (WER). A first level redundancy buffer (e1 buffer) is couple to the memory array. The e1 buffer may store data words that have failed verification or have not been verified. The e1 buffer may transfer data words to another dynamic redundancy buffer (e2 buffer). The e1 buffer may transfer data words that have failed to write to a memory array after a predetermined number of re-write attempts. The e1 buffer may also transfer data words upon power down.

Abstract: Dynamic redundancy registers for use with a device are disclosed. The dynamic redundancy registers allow a memory bank of the device to be operated with high write error rate (WER). A first level redundancy register (e1 register) is couple to the memory bank. The e1 register may store data words that have failed verification or have not been verified. The e1 register may transfer data words to another dynamic redundancy register (e2 register). The e1 register may transfer data words that have failed to write to a memory bank after a predetermined number of re-write attempts. The e1 register may also transfer data words upon power down.

Abstract: A memory management method and a storage controller are provided. The memory management method includes: dividing a plurality of word lines of a first block into a plurality of word line groups and recording a characteristic value for each of the word line groups; accumulating the characteristic values of a second word line group and a third word line group when reading a first word line group, wherein the second word line group and the third word line group are directly adjacent to the first word line group; and reading the second word line group via a first optimal read voltage group when the characteristic value of the second word line group is greater than a first threshold, wherein the first optimal read voltage group is different from a default read voltage group corresponding to the second word line group.

Abstract: A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words and associated memory addresses into a cache memory, and wherein each data word of the second plurality of data words is associated with a pending operation. Additionally, the method comprises detecting a power up signal and responsive to the power up signal, transferring the second plurality of data words and associated memory addresses from the secure memory storage area to the cache memory. Finally, responsive to the transferring, and before the memory device is powered up, the method comprises processing the second plurality of data words and associated memory addresses from the cache memory to the pipeline for writing data to the memory bank during power up.

Abstract: A Magnetic Random Access Memory apparatus device having a memory element formed as a magnetic tunnel junction (MTJ) pillar and having a heating element for maintaining a desired minimum temperature of the memory element. The heating element is separated from the memory element by a thin, non-magnetic, electrically insulating wall, which can be constructed of alumina. The heating element is connected with circuitry that controllably delivers electrical current to the heating element to maintain a desired minimum temperature of the memory element.

Abstract: According to one embodiment, a magnetic memory device includes a first magnetic portion, a first magnetic layer, a first nonmagnetic layer, a second magnetic portion, a second magnetic layer, a second nonmagnetic layer, a first electrode, and a second electrode. The first magnetic portion includes a first magnetic part and a second magnetic part. The first nonmagnetic layer is provided between the first magnetic layer and the first magnetic part. The second magnetic portion includes a third magnetic part and a fourth magnetic part. The second nonmagnetic layer is provided between the second magnetic layer and the third magnetic part. The first electrode electrically is connected to the second magnetic part and the fourth magnetic part. The second electrode is electrically connected to the first magnetic part and the third magnetic part.

Abstract: The present disclosure is directed to a device, a method, and a non-transitory computer readable medium for determining a level of uncertainty of programmed states of memory cells. In one aspect, a memory device includes memory cells, an uncertainty prediction circuit coupled to the memory cells, and a data conversion circuit coupled to the memory cells. The uncertainty prediction circuit is configured to determine, from a subset of the memory cells coupled to a word line, a number of memory cells having a predetermined state. The data conversion circuit is configured to apply a data conversion to a portion of data stored by the subset of the memory cells, in response to the uncertainty prediction circuit determining that the number of memory cells is between a first threshold and a second threshold.

Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to voltage detection with correlated electron switch devices.

Abstract: The present disclosure provides a flash memory device including a flash memory comprising a plurality of nonvolatile memory cells, divided into a plurality of erase units; a memory section dedicated to storing erase status information, the erase status information indicating an erase status of the plurality of erase units; and a memory controller configured to receive an erase request indicating at least one erase unit; store erase status information for the at least one erase unit in the memory section; perform an erase operation on the at least one erase unit; and update the stored erase status information upon completion of the erase operation. In addition, the present disclosure provides a way how incomplete erase commands can be handled transparently in a fail safe way.

Abstract: Example methods and mechanisms are described herein for implementing and adiabatically operating a topological quantum computing (TQC) phase gate that complements the existing Clifford operations, and thereby allows universal quantum computation with Majorana systems. Further embodiments include a testing system for the phase gate that is feasible with Majorana zero modes and demonstrates violations of the CHSH-Bell inequality. Further, the design used for the testing of the inequality leads directly to a practical platform for performing universal TQC with Majorana wires in which explicit braiding need never occur.

Abstract: Optimized writing techniques for nonvolatile memory are presented. A microcontroller switches between a first writing mode and a second writing mode to write data to the nonvolatile memory. The switching between the first writing mode and the second writing mode depends on a first accumulated amount of data written to the nonvolatile memory in the first writing mode, or a number of spare blocks of the nonvolatile memory that is evaluated after a garbage collection procedure.

Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.