Abstract: A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words into an error buffer associated with the memory bank wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. Additionally, the method comprises monitoring an occupancy level of the error buffer and determining if the occupancy level of the error buffer has increased beyond a predetermined threshold. Subsequently, responsive to a determination that the occupancy level of the error buffer has increased beyond the predetermined threshold, increasing a write voltage of the memory bank, wherein subsequent write operations are performed at a higher write voltage.

Abstract: Provided herein may be a memory controller and a method of operating the same. The memory controller may include a control component configured to control an operation of a semiconductor memory device including a plurality of memory cells in response to a request from a host. The control component may be configured to select a subset of memory cells, among all memory cells in a selected page of the semiconductor memory device, and to determine an optimal read voltage based on the select subset of memory cells.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

Abstract: Systems and methods for wire feed speed control are disclosed. An example welding power supply includes a control panel comprising one or more input elements, and control circuitry. The control panel is configured to receive a first input relating to a material thickness and receive a second input to place the welding power supply in a first mode of operation, wherein the first input relates to a wire diameter. The control circuitry is configured to place the welding power supply in the first mode of operation when the first input is received from the one or more input elements; determine a coarse wire feed speed when the welding power supply is in the first mode of operation; receive a third input to fine tune the coarse wire feed speed; and fine tune the coarse wire feed speed based on the received third input.

Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.

Abstract: A refresh control device, and a memory device may be provided. The latch controller may include a first oscillator configured to generate a first oscillation signal, and a second oscillator configured to generate a second oscillation signal. The latch controller may be configured to receive a precharge signal and prevent the second oscillation signal from being synchronized with the precharge signal.

Abstract: A method for programming a ReRAM cell including a ReRAM device connected in series with an access transistor includes biasing the ReRAM cell with a programming potential that configures the access transistor in a common-source configuration and applying at least one programming voltage pulse to a gate of the access transistor, the programming voltage pulse having a magnitude selected to limit programming current to a preselected value.

Abstract: A tunable resistive element, comprising a first terminal, a second terminal, a dielectric layer and an intercalation layer. The dielectric layer and the intercalation layer are arranged in series between the first terminal and the second terminal. The dielectric layer is configured to form conductive filaments of oxygen vacancies on application of an electric field. The intercalation layer is configured to undergo a topotactic transition comprising an oxygen intercalation in combination with a change in the resistivity of the intercalation layer. A related memory device and a related neuromorphic network comprise resistive memory elements as memory cells and synapses respectively and a corresponding design structure.

Abstract: A static random access memory (SRAM) array is provided. The SRAM array includes a first bit cell array, a second bit cell array, and a strap cell. The second bit cell array is arranged along a first direction. The strap cell is arranged along a second direction and is positioned between the first bit cell array and the second bit cell array along the first direction. The strap cell includes an H-shaped NW region, an H-shaped PW region, and a deep N-type well (DNW) region. The H-shaped NW region and the H-shaped PW region each includes two strip portions extending along the first direction and a linking portion extending along the second direction. Two terminals of the linking portion are in contact with the two strip portions.

Abstract: A resistive memory device and a fabricating method thereof are provided. The resistive memory device includes: a first electrode electrically coupled with a first wire; a second electrode facing the first electrode and electrically coupled with a second wire, the second electrode including an oxygen vacancy reservoir and a contact electrode; and a memory cell including a variable resistive layer and being disposed between the first electrode and the second electrode. The variable resistive layer has a conductive filament, which includes oxygen vacancies and connects the first electrode and the second electrode. The oxygen vacancy reservoir is disposed on the variable resistive layer, and the contact electrode is coupled to the oxygen vacancy reservoir and the second wire. The oxygen vacancy reservoir has a volume or oxidizing power to exchange a limited amount of oxygen ions and oxygen vacancies required for switching the conductive filament with the variable resistive layer.

Abstract: A three-dimensional (3D) memory device having a plurality of vertical channel structures includes a first memory block, a second memory block, and a bit line. The first memory block includes first vertical channel structures extending in a vertical direction with respect to a surface of a substrate. The second memory block includes second vertical channel structures on the first vertical channel structures in the vertical direction and first and second string selection lines extending in a first horizontal direction and offset in the vertical direction. The bit line extends in the first horizontal direction between the first and second memory blocks and is shared by the first and second memory blocks. The second memory block may include first and second string selection transistors which are each connected to the bit line and the first string selection line and have different threshold voltages from each other.

Abstract: An apparatus may include: a memory device suitable for writing data while erasing at least one monitor cell among a plurality of memory cells in a write mode, and reading the at least one monitor cell by supplying a monitor voltage in a monitor mode; and a controller suitable for transmitting a monitor command and address information for reading the at least one monitor cell to the memory device in the monitor mode, and determining whether to perform a reclaim operation based on the values of the at least one monitor cell read by the memory device.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for constructing and programming quantum hardware for quantum annealing processes.

Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.

Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a read operation or a particular write operation may be performed on a correlated electron switch (CES) device by coupling a terminal of the CES device to a particular node through any one of multiple different resistive paths.

Abstract: A memory apparatus may be provided. The memory apparatus may include a global bit line configured to receive a drift current. A voltage clamping circuit configured to limit a voltage level of the global bit line.

Abstract: A semiconductor device includes: first and second terminal switches connected correspondingly between the first and second terminals of a sense amplifier and corresponding first and second nodes; first and second recycle switches connected correspondingly between the first and second nodes and corresponding third and fourth nodes; and first and second capacitors connected correspondingly between the third and fourth nodes; and wherein the first and second recycle switches are configured to selectively connect the first and second capacitors correspondingly to the first and second nodes in phases including as follows: during a recovery phase in which first and second gleaned amounts of charge (first and second gleaned charges) are recovered from corresponding selected ones of bit lines; and during a reuse phase in which the first and second gleaned charges are reused from correspondingly onto selected corresponding ones of the array of bit lines.

Abstract: Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.

Abstract: An operating method of a resistive memory element includes: performing a thermal step on the resistive memory element; performing a set and reset cycle operation on the resistive memory element to increase a read margin of the resistive memory element after a thermal step; and determining whether the resistive memory element passes a read margin verification.

Abstract: An electronic device configured for real-time calibration of an on-board accelerometer. A plurality of acceleration measurements are collected from the accelerometer to form a data set. An accelerometer error correction model is maintained that includes bias error calibration parameters, sensitivity calibration parameters, and cross-axis calibration parameters that each specify respective weights for each of bias error, sensitivity error, and cross-axis error. Calibration values are determined for one or more of the bias error calibration parameters, the sensitivity calibration parameters, and the cross-axis error calibration parameters for the data set of acceleration measurements using the accelerometer error correction model. A true acceleration vector may be determined that corresponds to a subsequently received acceleration measurement using the determined calibration values.