Abstract: Methods and apparatus for processing signals captured by one or more sensors are disclosed. An example method includes receiving a first signal from a control circuit, the first signal including control data associated with the one or more sensors, recovering a fixed frequency clock signal and a control signal from the first signal, generating a spread spectrum clock signal based on the fixed frequency clock signal, receiving a sensor data signal based at least in part on data captured by the one or more sensors, the spread spectrum clock signal, and the control signal, retiming the sensor data signal based at least in part on the spread spectrum clock signal and the fixed frequency clock signal, and generating an output signal based on the retimed sensor data signal.

Abstract: The purpose of the present invention is to cause a reception side communication device to appropriately detect a start bit. A serial communication unit (100), which transmits serial data by a combination of a high level signal and a low level signal, is provided with: a serial communication part (111) that provides the start bit on the head of the serial data, and transmits the high level signal in a prescribed duration just before the start bit; and a duration setting part (113) that sets the duration.

Abstract: A communication system includes a master unit; and a plurality of slave units including a slave unit to which a termination resistance is set, the plurality of slave units connected to the master unit via a communication line. In the communication system, the master unit includes a master communication control unit that normally sets a communication rate of communication performed with the plurality of slave units to a high baud rate, switches the high baud rate to a low baud rate after detecting that communication with the slave unit to which the termination resistance is set is disabled, transmits an instruction for switching the low baud rate to the high baud rate to the plurality of slave units after detecting that the communication with the slave unit to which the termination resistance is set is restored, and switches setting of the master unit itself to the high baud rate.

Abstract: A network interface module for coupling a host device to a switched network as a network node is described. The network interface module comprises a single half-duplex port for communicatively coupling to a shared bus of the switched network, at least one frame queue sized to store one multicast read frame received via the shared bus, and logic circuitry. The logic circuitry is configured to decode a read command for the interface module included in a payload of the multicast read frame that includes multiple read commands for other network nodes of the switched network, and transmit a response frame including read data on the shared bus when detecting the shared bus is available for transmitting.

Abstract: There are provided a substrate; a main body case; and a first locking member and a second locking member for fixing the substrate and the main body case, the substrate includes a first receptacle connector configured to be coupled to a first plug of a first cable, a second receptacle connector configured to be coupled to a second plug of a second cable, a first coil that supplies electric power to the first receptacle connector, and a second coil that supplies electric power to the second receptacle connector, a distance from the first locking member to the first coil is shorter than a distance from the first locking member to the first receptacle connector, and a distance from the second locking member to the second coil is shorter than a distance from the second locking member to the second receptacle connector.

Abstract: An equalization time configuration method is applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used. The equalization time configuration method includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

Abstract: A data storage device and method for lane detection and configuration are provided. In one embodiment, a data storage device is provided comprising a memory, an interface, and a controller. The controller is configured to detect whether a cable coupled with the interface is providing a first channel configuration signal that indicates that the cable is in a first cable orientation or a second channel configuration signal that indicates that the cable is in a second cable orientation. In response to detecting that the cable is not providing either the first or the second channel configuration signal, the controller uses a default lane configuration to communicate with the host via the cable. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in an output of the clock gating circuit. The clock gating circuit is disabled when an output of the counter indicates a preconfigured maximum count value. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received over the one-wire bus ignores edges in the data signal while the counter output has a value that is less than the maximum count value, and resets the counter in response to an edge detected in the data signal received over the one-wire bus.

Abstract: A method includes detecting, by a coexistence controller of a system on a chip (SoC), an occurrence of a coexistence event of an SoC component; providing, by the coexistence controller, an indication of the occurrence of the coexistence event to a coexistence coordinator; and changing, by the coexistence controller, an operating point of the SoC from a current operating point to a new operating point responsive to receiving an operating point change request from the coexistence coordinator.

Abstract: A system for increasing the speed and reducing the time to obtain a required amount of data, from a secondary storage device, for a digital computer, BASED UPON measures to improve the time efficiency of I/O request processing by improving the timing and sequence of transfers, thus improving the efficiency of mass storage devices.

Abstract: An interconnected computer system includes a Peripheral Component Interconnect Express (PCIe) fabric, a first computer system communicatively coupled to the PCIe fabric, a second computer system communicatively coupled to the PCIe fabric, and a shared single-access hardware resource coupled to the PCIe fabric. The first computer system includes a first processor and first memory coupled to the first processor configured to store a first flag indicating a desire of the first computer system to access the shared single-access hardware resource and a turn variable indicating which of the first computer system and the second computer system has access to the shared single-access hardware resource. The second computer system includes a second processor and second memory coupled to the second processor configured to store a second flag indicating a desire of the second computer system to access the shared single-access hardware resource.

Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A primary device coupled to the SPI bus can generate read or write instructions for a secondary device. In response to instructions from the primary device, the secondary device can prepare a response. The response message can include a secondary device status field to indicate a readiness of the secondary device to provide a particular data payload to the primary device. Using deferrals that are communicated from the secondary device to the primary device can enable longer latency SPI operations to proceed without monopolizing the SPI bus.

Abstract: A device for a serial bus system. The device includes a reception block for receiving a signal from a bus of the bus system. The signal is based on a transmission signal via which a message is exchanged between user stations. The reception block receives, in a first communication phase, the signal using a first reception threshold, and in a second communication phase, receives the signal using a second reception threshold. The device includes an evaluation block for evaluating the signal from the bus using a switchover reception threshold that differs from the first and second reception thresholds, and a reception threshold switching block for the time-limited switchover of the reception threshold of the reception block from the first reception threshold to the second reception threshold when the evaluation block detects the bus level for data of the transmission signal, using the switchover reception threshold in the signal.

Abstract: Disclosed are techniques for chip-to-chip (C2C) serial communications, such as communications between chiplets on a multi-chip package. In some aspects, a method of on-die monitoring of C2C links comprises detecting a change of the C2C link from a first link state to a second link state and storing link state change information in an on-die first-in, first-out (FIFO) buffer. The link state change information indicates the first link state, the duration of time the C2C link was in the first link state, and the speed of the C2C link in the first link state. Upon detecting a request for link state change information, link state change information is retrieved from the FIFO buffer and transmitted serially to an output pin of the die, such as a general purpose input/output (GPIO) pin.

Abstract: Systems and methods for chip operation using serial peripheral interface (SPI) with reduced pin options contemplate eliminating the chip select pins, interrupt pins and/or reset pins for host (also referred to as master)-to-device (also referred to as slave) communication links, while preserving the possibility of backward compatibility for legacy devices if desired. The communication link may include a clock line, a host-to-device line, and a device-to-host line. The host may use specific sequences of signals on the clock and host-to-device line to provide start and stop sequence commands, interrupts, or reset commands. By consolidating these commands onto the clock and host-to-device line, pin count may be reduced for portions of the host and slave circuits. Likewise, fewer (or at least shorter potentially) conductive traces may be needed to interconnect the host to the device. Such changes may save cost, make layout design easier, and/or save space within a computing device.

Abstract: The present disclosure discloses a server management framework and a server. The server management framework includes: a management board, wherein the management board comprises a baseboard management controller, a platform controller hub, and a management board complex programming logic device (CPLD), and a first end of the management board CPLD is connected to the platform controller hub; and a motherboard, wherein the motherboard comprises a central processing unit and a motherboard CPLD, a first end of the motherboard CPLD is connected to the central processing unit, and a second end of the motherboard CPLD is connected to a second end of the management board CPLD, so that the baseboard management controller communicates with the management board CPLD through the motherboard CPLD, and the platform controller hub communicates with the baseboard management controller through the motherboard CPLD and the management board CPLD.

Abstract: Provided are a Peripheral Component Interconnect Express (PCIe) interface device and a method of operating the same. The PCIe interface device includes a first buffer, a second buffer, and a buffer controller. The first buffer may be configured to store a plurality of first transaction layer packets received from multiple functions. The second buffer may be configured to store a plurality of second transaction layer packets received from the multiple functions. The buffer controller may be configured to, when a first buffer of a switch is full, realign an order in which the plurality of second transaction layer packets are to be output from the second buffer to the switch, based on IDs of the plurality of second transaction layer packets.

Abstract: Disclosed is a signal processing circuit, a contactless connector, a signal processing method and a storage medium.

Abstract: A communication device mounted in each of a plurality of information processing devices connected to a fabric, the communication device comprises: a serial interface that transmits and receives a first packet compliant with a Peripheral Component Interconnect Express (PCIe) standard; a requester unit that acquires the first packet from the serial interface and converts the first packet that has been acquired into a second packet that is transmitted and received via the fabric among a plurality of the information processing devices sharing a memory space that is virtually extended by using a device identifier specific to each of the information processing devices; a fabric communication unit that transmits and receives the second packet via the fabric; and a completer unit that acquires the second packet from the fabric communication unit and generating a response packet to a request included in the second packet that has been acquired.

Abstract: An audio and video transmission system includes a multimedia device. The multimedia device includes a high-definition multimedia interface (HDMI) receiver, a first transfer circuit, and a first universal serial bus type C (USB-C) interface. The first transfer circuit is configured to transfer a first audio signal output by an audio channel pin of the HDMI receiver into a second audio signal in a universal serial bus (USB) interface format. The first USB-C interface is configured to transmit the second audio signal. The HDMI audio channel pin is an audio return channel (ARC) pin or an enhanced ARC pin.