Abstract: In an embodiment, a system includes a contactless reader and an apparatus. The apparatus includes a contactless transponder including a contactless interface and a transponder wired interface and being configured to communicate with a contactless reader according to a contactless protocol through the contactless interface. The apparatus includes a bus coupled to the transponder wired interface, and at least one module coupled to the bus, the at least one module including a processing circuit, the contactless reader being configured to communicate instructions of a software program executable by the processing circuit to the at least one module through the contactless transponder.

Abstract: A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root I/O virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.

Abstract: An USB multiplexing single-wire interface unit comprises a D+ pin, a D? pin, a control bit register for USB and single-wire interface modes and a USB controller, the USB controller comprises an EOP detection module and a single-wire interface EOP detection module. The USB mode or the single-wire interface mode is selected according to mode identification of the control bit register for USB and single-wire interface modes, an output of the EOP detection module is selected as a USB EOP trigger signal in the USB mode, and an output of the single-wire interface EOP detection module is selected as a USB EOP trigger signal in the single-wire interface mode.

Abstract: Embodiments of systems and methods for high-speed Out-of-Band (OOB) management links for inter-Baseboard Management Controller (BMC) communications in High Performance Computing (HPC) platforms are described. In some embodiments, an HPC platform may include: a system BMC; and an accelerator tray comprising: (a) one or more managed subsystems, (b) a tray BMC coupled to the one or more managed subsystems, and (c) a Field-Programmable Gate Array (FPGA) coupled to the tray BMC and to the system BMC.

Abstract: Devices for performing communications are disclosed. In some implementations, a device includes: an upstream port for receiving data from or transmitting data to one or more external devices located on an upstream path through a link including a plurality of lanes; a lane margining controller coupled to the upstream port and for transmitting, via the upstream port, to the one or more external devices, a margin command for requesting a lane margining operation to acquire margin status information to indicate a margin of each of the plurality of lanes, and controlling the upstream port to receive the margin status information from the external devices; and a port setting controller coupled to be in communication with the upstream port to receive the margin status information and for determining a setting of the upstream port based on the margin status information.

Abstract: A standalone Storage Controller with PCIe Multi-Mode capability that can be configured as PCIe Root-Complex (RC), an End-Point (EP) or a bridge (BR). In EP mode, the Storage Controller acts like a regular PCIe slaved controller which is connected to a PCIe Root-Complex provided by a Host via a PCIe port. While in RC mode, the Storage Controller acts as a PCIe configuration and management entity, a Host acting as a PCIe Root-Complex, which an add-in card or chip can attach to via a PCIe port that is provided by the Storage Controller, supporting any type of Network Device Interface, without an external Root-Complex. While in bridge mode, the Storage Controller can act as a transparent or non-transparent bridge with either a Root-Complex or End-Point port for the internal connection to the bridge.

Abstract: Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array.

Abstract: A user station for a serial bus system. The user station includes a receiver for receiving a signal from a bus of the bus system, and a device for evaluating the reception signal that is output by the receiver. The receiver generates a digital reception signal from the signal received from the bus and to output the signal to the device at a terminal. The device evaluates the digital reception signal with regard to a predetermined communication protocol that establishes when a predetermined communication phase, which indicates a subsequent transfer of useful data in a message, begins and ends. The device reverses the data flow of the digital reception signal to the receiver at the terminal for a time period of at least one bit if the evaluation of the device shows that data at that time are being received from the bus in the predetermined communication phase.

Abstract: The present disclosure relates to systems, methods, and computer-readable media for establishing and managing a trusted connection between a peripheral device and a client device. For example, systems discussed herein include determining whether a peripheral device poses a security risk based on a combination of peripheral device data and a client profile including environmental data and historical usage data for the client device. Systems described herein may further grant a level of trust based on the determine security risk. The systems disclosed herein facilitate implementation of intelligent policies that are user friendly without exposing the client device to a variety of security threats.

Abstract: Disclosed are embodiments that provide digital data communication between a single-pair Ethernet and a multi-pair Ethernet. Some embodiments include a single-pair Ethernet interface that is configured to operate in at least two modes. In a first mode, the single-pair Ethernet interface operates in a conventional manner. In a second mode, alternate pin configurations are employed to provide a low-cost interoperability between a single-pair Ethernet interface and a multi-pair Ethernet interface. For example, in the second mode, the single-pair Ethernet receives, via a first receive data pin, from a first transmit data pin of the multi-pair Ethernet interface, a data signal, and receives, via a second receive data pin, from a second transmit data pin of the multi-pair Ethernet interface, a second data signal.

Abstract: An apparatus includes an interface circuit adapted to couple the apparatus to a serial bus, a slot counter, and a processor. The slot counter may be configured to monitor a radio frequency coexistence management cycle that includes a plurality of time slots. The processor may be configured to transmit a first datagram through the interface circuit during a first time slot in the plurality of time slots. The apparatus may be uniquely permitted to initiate transactions over the serial bus during the first time slot. The processor may be further configured to participate in an arbitration procedure during a second time slot in the plurality of time slots. More than one device coupled to the serial bus may be permitted to initiate transactions in the second time slot.

Abstract: A charge pump has a first branch that includes a first node connected between a first pull-up switch and a first pull-down switch and a second branch that includes a second node connected between a second pull-up switch and a second pull-down switch. The second branch is connected in parallel with the first branch. The charge pump has a voltage equalization circuit to equalize a first voltage at the first node and a second voltage at the second node. A third branch includes a third node that is connected between a third pull-up switch and a third pull-down switch. The third node is connected to the second node. The third pull-up switch and the first pull-up switch are controlled by a common pull-up signal. The third pull-down switch and the first pull-down switch are controlled by a common pull-down signal.

Abstract: A memory controller includes a host interface circuit connectable to a host device by a bus conforming to a memory card system specification, a data buffer circuit including a buffer memory, a tag information generation circuit configured to generate tag information associated with a command received by the host interface circuit, and a first register in which the tag information generated by the tag information generation circuit is stored, and a second register into which the tag information stored in the first register is copied after the command is fetched from the host interface circuit for processing. When a read request is made from the host interface circuit to the data buffer circuit, the data buffer circuit returns read data stored in the buffer memory upon confirming that the tag information stored in the first register and the tag information stored in the second register match each other.

Abstract: An information processing system includes a host and a storage device that transmits a first pulse signal to the host and receives a second pulse signal from the host through a transmission line. The storage device has a first register to store a value of a first parameter and correction circuit to adjust a first duty ratio of the first pulse signal according to the value of the first parameter. The host includes a first calibration processor that measures a plurality of the first duty ratios as output from the storage device for different values of the first parameter to derive a first optimum value based on the measured first duty ratios and transmit the derived first optimum value to the storage device as the value of the first parameter to be stored in the first register.

Abstract: A transceiver has a first interface supplied by a first supply voltage to interface with external devices operating in a first supply domain and a second interface supplied by a second supply voltage and adapted to interface to an external communication bus operating in a second supply domain. The transceiver has a first internal communication link, which is adapted to transfer transmit data generated by an external device operating in the first supply domain, from the first interface to the second interface, and a second internal communication link, which is adapted to transfer transmit data be supplied from the external communication bus operating in the second supply domain from the second interface to the first interface.

Abstract: Devices and methods are disclosed for detecting which of a multiple ports of a storage device is connected to a host system using a shared detection line. In certain embodiments, a storage device includes non-volatile memory, a first data port, a second data port having a faster data transfer speed, a shared detection line, and control circuitry. The control circuitry can be configured to detect voltage on the shared detection line in response to a connection of at least one of the first data port and the second data port to the host system, determine which of the first data port or the second data port is connected to the host system, and establish a data connection with the host system at the first data transfer speed or the second data transfer speed based on the port connected to the host system.

Abstract: The present disclosure generally relates to a method and device for accessing more dies per channel in a data storage device. Each flash interface module (FIM) can have any number of bus multiplexers coupled thereto, and each bus multiplexer can have any number of memory devices coupled thereto. The bus multiplexers can be connected in series or in parallel to the FIM. The individual bus multiplexers can be addressed by a chip enable (CE) command that identifies the specific bus multiplexer as well as the specific memory device of the specific bus multiplexer. The information in the CE command allows more dies per channel without creating signal interference (SI) or limiting transmission performance.

Abstract: A system for controlling data communications, comprising an enclosure management processor configured to generate a peripheral component interconnect express reset command and a chip reset command. A re-timer configured to receive the peripheral component interconnect express reset command and the chip reset command and to control a communications port in response to the peripheral component interconnect express reset command and the chip reset command. The communications port configured to reset in response to a control signal from the re-timer.

Abstract: An embodiment includes a system comprising: a first shield board that includes first and second connectors; wherein the first connector of the first shield board is configured to communicate with a first connector of a second shield board via a cable; wherein the first shield board has connectors configured to directly couple to connectors of a first base board; wherein the first shield board is configured to communicate data and power to the second shield board via the first connector of the first shield board, the cable, and the first connector of the second shield board. Other embodiments are addressed herein.

Abstract: Systems, devices, computer program products, and methods include determining by a connection manager that a connected device can be enhanced by an asymmetrical multi-lane link. The connection manager can use system parameters, including bandwidth information, to switch a direction of one or more lanes of the multi-lane link. The connection manager can use register setting instructions to change register settings on the host side and on the device side to switch the direction of one or more lanes of the multi-lane link.