Abstract: Aspects of the embodiments are directed to a port comprising hardware to support the multi-lane link, the link comprising a lane that comprises a first differential signal pair and a second differential signal pair. Link configuration logic, implemented at least in part in hardware circuitry, can determine that the port comprises hardware to support one or both of receiving data on the first differential signal pair or transmitting data on the second differential signal pair, and reconfigure the first differential signal pair to receive data with the second differential signal pair or reconfigure the second differential signal pair to transmit data with the first differential signal pair; and wherein the port is to transmit data or receive data based on reconfiguration of one or both the first differential signal pair and the second differential signal pair.

Abstract: A high speed intelligent network recorder for recording a plurality of flows of network data packets into and out of a computer network over a relevant data time window is disclosed. The high speed intelligent network recorder includes a printed circuit board; a high speed network switching device mounted to the printed circuit board; and an X column by Y row array of a plurality of intelligent hard drives with micro-computers mounted to the printed circuit board and coupled in parallel with the high speed network switching device.

Abstract: Traffic for USB devices that are connected to a USB-C dock can be adaptively prioritized. When the consumption of the bandwidth of a connection between a computing device and a USB-C dock exceeds a threshold, a filter driver can notify a service. The service can update device priority values for the devices that are connected to the USB-C dock based on applications that are accessing the devices. The service can relay the updated device priority values to the filter driver. The filter driver can then attempt to reduce bandwidth consumption by changing device settings of any device with a lower priority value, and then, if changing device settings is insufficient, may attempt to reduce bandwidth consumption by lowering the priority of the device's traffic.

Abstract: A circuit has a driver circuit with a slew-rate controller, an output stage and a monitoring circuit. The output stage is connected to a first bus line and to a second bus line, and the driver circuit is designed to control the output stage on the basis of a first logic signal in such a manner that a corresponding bus voltage is produced between the first bus line and the second bus line. The slew-rate controller is coupled to the driver circuit and is designed to set a slew rate of the driver circuit on the basis of an input signal. The monitoring circuit is designed to generate the input signal for the slew-rate controller, wherein the input signal indicates a higher slew rate during an arbitration phase of a data frame contained in the first logic signal than during a data transmission phase of the data frame.

Abstract: A high speed intelligent network recorder for recording a plurality of flows of network data packets into and out of a computer network over a relevant data time window is disclosed. The high speed intelligent network recorder includes a printed circuit board; a high speed network switching device mounted to the printed circuit board; and an X column by Y row array of a plurality of intelligent hard drives with micro-computers mounted to the printed circuit board and coupled in parallel with the high speed network switching device.

Abstract: A device includes an arbiter circuit configured to receive a first request for a resource. The first request is associated with a first credit cost. The arbiter circuit is further configured to receive a second request for the resource. The second request is associated with a second credit cost. The arbiter circuit is further configured to select the first request for the resource as an arbitration winner. The arbiter circuit is further configured to decrement a number of available credits associated with the resource by the first credit cost. The arbiter circuit is further configured to, in response to the number of available credits associated with the resource falling to a lower credit threshold, wait until the number of available credits associated with the resource reaches an upper credit threshold to select an additional arbitration winner for the resource.

Abstract: A high speed intelligent network recorder for recording a plurality of flows of network data packets into and out of a computer network over a relevant data time window is disclosed. The high speed intelligent network recorder includes a printed circuit board; a high speed network switching device mounted to the printed circuit board; and an X column by Y row array of a plurality of intelligent hard drives with micro-computers mounted to the printed circuit board and coupled in parallel with the high speed network switching device.

Abstract: A configurable PCI card for connecting to a PCI interface is disclosed. The configurable PCI card comprises a bus interface disposed on a base card for communicatively connecting to a bus of a computing device. The configurable PCI card further comprises a bracket for physically securing the base card to the computing device. The configurable PCI card also comprises a wire layout disposed on the base card for replicating a plurality of different power and heat generation profiles that correspond to a plurality of different chipsets.

Abstract: In general, techniques are described for extensible mappings for vehicle system busses. A device configured to interact with a vehicle may perform the techniques. The device may comprise a memory that stores an extensible mapping between a local control message and a standard control message. The device may also include a processor configured to execute an operating system to control a system of the vehicle. The operating system may generate the standard control message, where the standard control message includes a first representation of a command set. The processor may translate, based on the extensible mapping, the standard control message to obtain the local control message, the local control message including a second representation of the command set. The processor may transmit, via a control bus coupled to the processor and the system, the local control message to initiate an operational state change of the system.

Abstract: An electronic device includes a device housing and at least two grip sensors disposed along the device housing. One or more processors are operable with the at least two grip sensors. At least one electronic latch is operable with the one or more processors. The one or more processors transition the at least one electronic latch from a latched state to an unlatched state when the at least two grip sensors detect a grip applied to the at least two grip sensors.

Abstract: A system can include memory circuits configured to execute memory access operations in response to commands, a serial interface circuit configured to receive commands, including at least a first type command, and a controller circuit configured to generate a command complete acknowledgement that is output at the interface circuit after an operation indicated by the first type command has been completed by the memory circuits.

Abstract: A connection interface conversion chip, a connection interface conversion device and an operation method are provided. The connection interface conversion chip includes a USB interface circuit, a DP interface circuit, a USB core circuit and a switching circuit. The USB interface circuit is suitable for coupling to a USB connector. The DP interface circuit is suitable for coupling to a DP connector. In a first operation mode, at least one USB signal pair received by the USB connector is transmitted to the USB core circuit through the USB interface circuit. The USB core circuit decodes the USB signal pair and generates DP data. The DP data is transmitted to the DP connector by the DP interface circuit. In a second operation mode, the DP data received by the USB connector is transmitted to the DP connector through the USB interface circuit, the switching circuit and the DP interface circuit.

Abstract: Methods, systems, and computer-readable media for batch registration and configuration of devices are disclosed. A plurality of devices are detected over one or more networks. Data indicative of the plurality of devices is provided through a user interface. Through the user interface, user input is received that indicates a selected plurality of the devices. The selected plurality of the devices are registered with a service provider environment. The selected plurality of the devices are authenticated using device-specific credentials and registered for device-specific accounts with the service provider environment. A configuration profile is deployed to the selected plurality of the devices.

Abstract: A chiplet system can include a Serial Peripheral Interface (SPI) bus for communication. A primary device coupled to the SPI bus can generate read or write instructions for a secondary device. In response to instructions from the primary device, the secondary device can prepare a response. The response message can include a secondary device status field to indicate a readiness of the secondary device to provide a particular data payload to the primary device. Using deferrals that are communicated from the secondary device to the primary device can enable longer latency SPI operations to proceed without monopolizing the SPI bus.

Abstract: A method carried out in a system, the system comprising at least a diagnosis plug-in device (1) connected to the diagnosis plug (8) of a vehicle, a host server (2), one or more on-board ECUs (3), the method comprising the following steps: /a/ detect a Bus Active condition, either via an electrical pin on the diagnosis plug or via an analysis of activity level on at least one Diagnosis bus accessible at the diagnosis plug, /b/ cause the diagnosis plug-in device to listen only on the at least one Diagnosis bus after the Bus Active condition is detected, /c/ determine a write enable condition, according to evolution of bus load level on the at least one diagnosis bus and/or after a certain time elapsed since Bus Active condition was true, /e/ whenever the write enable condition becomes true, carry out the request/answer services to write requests on the diagnosis bus and retrieve, in the corresponding answers, various data from the board ECUs (3), to be decoded and forwarded to a client fleet management system,

Abstract: A serial data processing device includes an offset detector circuit and an offset calibration circuit. The offset detector circuit is configured to store a plurality of tokens, and to receive a first data signal from a host device, and to detect an offset in the received first data signal according to the plurality of tokens, in order to generate a calibration signal, in which each of the tokens includes at least one predetermined logic value, and numbers of the at least one predetermined logic value in each of the plurality of tokens are different. The offset calibration circuit is configured to calibrate the received first data signal according to the calibration signal, in order to generate a second data signal.

Abstract: The disclosure relates to a transceiver and associated method and computer program. The transceiver comprises a transmitter for transmitting, based on an input signal, a transmitter output voltage to a differential signaling bus, the transceiver configured to: generate, from the input signal, a copy of the transmitter output voltage to provide an expected differential bus voltage; measure a differential bus voltage from the differential signaling bus; and detect an error frame on the differential signaling bus based on a comparison between the measured differential bus voltage and the expected differential bus voltage.

Abstract: An equalization time configuration method, applied to a processor system in which a Peripheral Component Interconnect Express (PCIe) bus or a Cache Coherent Interconnect for Accelerators (CCIX) bus is used, includes determining a working physical layer (PHY) type of a master chip and a working PHY type of a slave chip, determining an equalization time of the slave chip in a fourth phase of equalization based on the working PHY type of the master chip, and determining an equalization time of the master chip in a third phase of the equalization based on the working PHY type of the slave chip.

Abstract: Embodiments of the present disclosure relate to a system and a method for operating the system. The operating mode of a data processing circuit is changed according to a request indicating whether or not a first clock or a second clock is to be changed. Data transmitted from a first module to a second module inside the system is processed according to the operating mode of the data processing system. Accordingly, when the clock of one of modules included in the system changes, the module can quickly switch to a state in which the same can transmit/receive data to/from another module included in the system, and the performance of data transmission/reception between the modules included in the system can be optimized.

Abstract: In one embodiment, an apparatus includes: a peer-to-peer (P2P) control circuit to issue a P2P communication request to a bus master of a multi-drop interconnect to request authorization to send a P2P transaction to at least one slave device coupled to the multi-drop interconnect; a transmitter to transmit the P2P transaction to the at least one slave device when the bus master grants the authorization for the P2P transaction; and another transmitter to output the clock signal to the multi-drop interconnect during the P2P transaction. Other embodiments are described and claimed.