Abstract: Methods and devices for presenting an image in an atomic manner across a plurality of displays of a computer device from a single buffer shared by the plurality of displays may include synchronizing the plurality of displays of the computer device. The methods and devices may initiate an atomic present request to present an image frame on the plurality of displays including a first display and a second display, the atomic present request may identify at least a first display texture and a second display texture from a plurality of display textures stored in the single buffer corresponding to the image frame and that the first display texture corresponds to a first display and the second display texture corresponds to a second display. The devices and methods may transmit a bundled set of first image frame data and second image frame data from the single buffer to a display driver.

Abstract: To perform inter-pixel image processing with lower latency and higher speed. An image sensor includes: a pixel array unit in which pixels having a photoelectric conversion function are arranged in an array; an AD conversion unit configured to perform AD conversion processing on pixel signals output from the pixels in parallel for each column of the pixels of the pixel array unit; a memory unit configured to hold pixel signals of any number of rows subjected to AD conversion in the AD conversion unit for each column of the pixels; an inter-pixel image processing unit configured to read pixel signals of any rows and columns from the memory unit, and perform computing between the pixel signals in parallel for each column of the pixels; and an output circuit configured to control output, to an outside, of pixel signals output from the AD conversion unit and pixel signals output from the inter-pixel image processing unit. The present technology can be applied to, for example, a CMOS image sensor.

Abstract: An interactive display case having a first frame, a plurality of storage areas within the first frame, a second frame, and processing circuitry. The processing circuitry is configured to detect an object passing through the interior of the second frame, identify an area within the interior of the second frame in which the object passes, where the area corresponding to one of the storage areas, and generate interaction data corresponding to the identified area.

Abstract: An accelerated secondary display system comprising a display adapter with a display simulator, a host computer with host software, a client device with a screen and client software. The display simulator is configured to send display characteristics to the host computer. The host computer is configured to receive the display characteristics and render an image into a frame buffer. The host software is configured to cause the host computer to stream image data over a communication channel, the image data based on the image in the frame buffer. The client software is configured to receive the image data over the communication channel and present a copy of the image on the screen based on the image data.

Abstract: Techniques are disclosed relating to sharing an arithmetic logic unit (ALU) between multiple threads. In some embodiments, the threads also have dedicated ALUs for other types of operations. In some embodiments, arbitration circuitry is configured to receive operations to be performed by the shared arithmetic logic unit from the set of threads and issue the received operations to the shared arithmetic logic unit. In some embodiments, the arbitration circuitry is configured to switch to a different one of the set of threads for each instruction issued to the shared arithmetic logic unit. In some embodiments, the shared ALU is configured to perform 32-bit operations and the dedicated ALUs are configured to perform the same operations using 16-bit precision. In some embodiments, the shared ALU is shared between two threads and is physically located adjacent to other datapath circuitry for the two threads.

Abstract: A display apparatus includes a plurality of input terminals capable of receiving image signals, a first display part showing whether or not the input terminal accepts the image signal with respect to each input terminal of the plurality of input terminals, an image display unit that displays an image according to the image signal received by a selected input terminal selected from the plurality of input terminals on a display surface, and a second display part showing the selected input terminal.

Abstract: Techniques for graphics processing unit (GPU) partitioning for virtualization are described herein. In one or more implementations, a GPU partitioning manager of a host device obtains a request for a virtual machine having GPU functionality. In particular, the request specifies the GPU functionality in terms of different GPU capabilities. These different capabilities correspond to segments of a GPU model that represents GPU functionality and is used to govern interactions between virtual machines and GPUs. The GPU partitioning manager determines whether GPUs of the host device are available to satisfy the request based on the specified capabilities. If so, the GPU partitioning manager allocates a portion of the determined available GPUs to the virtual machine to configure the virtual machine with a GPU partition having the functionality. The virtual machine configured with the GPU partition can then be exposed to provide GPU-processed data to a GPU partition requestor.

Abstract: A method is described. The method includes repeatedly loading a next sheet of image data from a first location of a memory into a two dimensional shift register array. The memory is locally coupled to the two-dimensional shift register array and an execution lane array having a smaller dimension than the two-dimensional shift register array along at least one array axis. The loaded next sheet of image data keeps within an image area of the two-dimensional shift register array. The method also includes repeatedly determining output values for the next sheet of image data through execution of program code instructions along respective lanes of the execution lane array, wherein, a stencil size used in determining the output values encompasses only pixels that reside within the two-dimensional shift register array.

Abstract: According to various aspects, just-in-time system bandwidth changes may be implemented in hardware to optimize power consumption and performance in an electronic device. More particularly, in a periodic system associated with an electronic device, a bandwidth for a next frame may be configured during a current frame via software operating on the electronic device. Hardware associated with the periodic system may issue a bandwidth change request for the next frame when a current time reaches a bandwidth increase threshold in response to actual processing time associated with the current frame finishing prior to the bandwidth increase threshold, which may be defined relative to a timer deadline that defines when the next frame starts to process.

Abstract: The disclosed concepts provide a method to generate and use a compound shader object. A compound shader object includes a shader's intermediate representation (IR) and one or more binary modules; each binary module configured to execute on one type of graphics processing unit (GPU) with a specific input state. One method includes receiving, through a public application programming interface (API), a request to execute a shader from an user-level application. At the framework level, if the request corresponds to one of the prior compiled binary modules, that module may be passed to a GPU for immediate execution via a system private interface. If the request does not correspond to one of the binary modules, the shader's IR module may returned to the requesting user-level application (which module would then have to be compiled before it may be sent to the GPU).

Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, an apparatus comprises a processor comprising one or more cores, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication for whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, the data is to be accessed by the GPU without necessarily accessing the processor's cache coherence controllers.

Abstract: A method of optimizing a processing time of a simulation engine that executes to create a simulated experience for a user, includes the steps of identifying a number of components that comprise the simulated experience to be rendered for the user in a virtual reality environment; assigns execution of the plurality of components to at least two threads, where the at least two threads execute in parallel on a CPU to create the simulated experience, where the first thread processes a first portion of the components for components that require rapid execution to create a realistic experience within the simulated experience, and reduces a processing load of the first thread by assigning a second portion of the components to execute in a second thread, where the second portion requires less rapid execution than the first portion to create the realistic experience.

Abstract: A virtual server includes one or more processors that execute instructions to generate a virtual desktop, and generate an active virtual monitor and a paused virtual monitor for the generated virtual desktop. A first portion of the generated virtual desktop is assigned to the active virtual monitor, and a second portion of the generated virtual desktop is assigned to the paused virtual monitor. The active and paused virtual monitors each have a respective allocated memory. The amount of memory allocated for the paused virtual monitor is less than the amount of memory allocated for the active virtual monitor. A captured image of at least one of the first and second portions of the generated virtual desktop is provided for presenting on a physical monitor of a client device.

Abstract: An apparatus includes a memory, a first buffer, a second buffer, and a processing circuit. The memory may be configured to store data. The first buffer may be configured to store a plurality of kernel values fetched from the memory and present a first signal communicating the kernel values as stored. The second buffer may be configured to store a plurality of input tiles fetched from the memory and present a second signal communicating the input tiles as stored. The processing circuit may be configured to (i) receive the first signal and the second signal, (ii) calculate a plurality of intermediate values in parallel by multiplying the input tiles with a corresponding one of the kernel values, and (iii) calculate an output tile comprising a plurality of output values based on the intermediate values. The kernel values are generally fetched from the memory to the first buffer slower than the input tiles are fetched from the memory to the second buffer.

Abstract: An apparatus and method are described for performing virtualization using virtual machine (VM) sets. For example, one embodiment of an apparatus comprises: graphics processing unit (GPU) to process graphics commands and responsively render a plurality of image frames; a hypervisor to virtualize the GPU to share the GPU among a plurality of virtual machines (VMs); and VM set management logic to establish a plurality of VM sets, each set comprising a plurality of VMs, the VM set management logic to partition graphics memory address (GMADR) space across each of the VM sets but to share the GMADR space between VMs within each VM set.

Abstract: Disclosed in the present specification is a wearable terminal for resolving limitation of a narrow display. The wearable terminal, according to the present specification, comprises: a band to be worn on a main body and the wrist; a display unit provided on the main body; and a control unit for controlling so that the content of an event is displayed on the display unit when the event occurs, wherein the control unit can run a normal mode and a special mode depending on the situation of a user, and is capable of controlling so that the content of the event is displayed on the display unit according to the situation of the user when the event has occurred in the special mode.

Abstract: A display includes eight modules. A relay group includes eight relays provided for the respective modules. Each relay includes: a buffer; a memory writer for writing video data into the buffer; and a memory reader that, after the memory writer completes writing, reads the video data from the buffer at a speed lower than a speed of the writing and outputs the read video data to the corresponding module. A video data supplier sequentially sorts the video data to the eight relays in such a manner that, per line of line data, the line data from the buffer of one relay of the eight relays is read during a writing period of the line data to buffers of the other seven relays.

Abstract: System on chip comprising a general purpose processing element, a graphics processing unit and a display interface, supporting graphics visualization on mobile computing devices and on embedded systems.

Abstract: A method for implementing a hybrid scalable CPU/GPU rigid body pipeline. The method includes partitioning a rigid body pipeline into a GPU portion comprising GPU components and a CPU portion comprising CPU components. The method further includes executing the GPU components on the GPU of a computer system, and executing the CPU components on the CPU of the computer system. Communication data dependencies between the CPU and the GPU are managed as the GPU components and the CPU components process through the GPU and the CPU. The method concludes by outputting a resulting processed frame for display.

Abstract: A method for extracting display data from a computing resource of a computer system comprises the dynamic selection of a display capturing mode among a plurality of display capturing modes.