Abstract: An embodiment of the invention may include a method, computer program product and system for operating an electronic display device. An embodiment may include displaying, using a first refresh rate, first content on a first partition of a display area of the electronic display device. An embodiment may include displaying, using a second refresh rate, second content on a second partition of the display area of the electronic display device. The first refresh rate is different from the second refresh rate.

Abstract: Technologies for dividing work across one or more accelerator devices include a compute device. The compute device is to determine a configuration of each of multiple accelerator devices of the compute device, receive a job to be accelerated from a requester device remote from the compute device, and divide the job into multiple tasks for a parallelization of the multiple tasks among the one or more accelerator devices, as a function of a job analysis of the job and the configuration of each accelerator device. The compute engine is further to schedule the tasks to the one or more accelerator devices based on the job analysis and execute the tasks on the one or more accelerator devices for the parallelization of the multiple tasks to obtain an output of the job.

Abstract: Methods and systems for reducing power consumption of a display link by compacting image data to allow the display link to be deactivated for a longer duration. For instance, pixels that correspond to a preset or default value for a display may be omitted from pixel data sent over the display link. Additionally or alternatively, the display link may be divided into multiple lanes that function independently so that a lane of the display link may be deactivated while other lanes are actively transmitting image data.

Abstract: Embodiments improve processing of data by determining if a read-modify-write operation on a frame is necessary or not. Some frames may be converted into a block of 8 bpp data. There may be no need to read the destination since the unnecessary pixels may be protected by the byte-enables. The burst write transfer may be performed for the entire frame when it is 8 bpp depth. An original transfer frame may be split into smaller portions of the frame. One or more of the smaller frame portions may be converted into byte alignment thus obviating the need for the read function to be performed on the smaller frame portions. Accordingly, significant bits of data are no longer processed under this operation which speeds up the overall processing of data. Portions of transfer frames that may not be converted to 8 bpp may be processed with read-modify-write operations.

Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.

Abstract: A memory management system for generating 3-dimensional computer images is provided. The memory management system includes a device for subdividing an image into a plurality of rectangular areas, a memory for storing object data pertaining to objects in the image which fall in each rectangular area, a device for storing the object data in the memory, a device for deriving image data and shading data for each rectangular area from the object data, a device for supplying object data for each rectangular area from the respective portion of the memory and, if the rectangular area contains objects also falling in at least one other rectangular area, also from the global list, to the deriving device, and a device for storing the image data and shading data derived by the deriving device for display. The memory includes at least one portion allocated to each rectangular area and at least one portion allocated as a global list.

Abstract: Remote desktop servers include a display encoder that maintains a secondary framebuffer that contains display data to be encoded and transmitted to a remote client display and a list of display primitives effectuating updated display data in the secondary framebuffer. The display encoder submits requests to receive the list of drawing primitives to a video adapter driver that receives and tracks drawing primitives that, when executed, update a primary framebuffer.

Abstract: A system and method for distributed computing including a compute node having a graphics processing unit (GPU) to execute tasks of a distributed computing job. A distributed-computing programming framework executes the tasks on the compute node. A GPU-daemon process shares GPU resources between the tasks executing on the GPU of the compute node.

Abstract: Methods, systems, and computer-readable media for interaction monitoring for virtualized graphics processing are disclosed. Execution of an application is initiated on a virtual compute instance that is implemented using CPU and memory resources of a server. Instruction calls are produced by the execution of the application and sent from the server to a graphics server over a network. The graphics server comprises a physical GPU, and a virtual GPU is implemented using the physical GPU and attached to the virtual compute instance. GPU output is generated at the graphics server based at least in part on execution of the instruction calls using the virtual GPU. A log of interactions between the application and the virtual GPU is stored. The interactions comprise the instruction calls sent to the graphics server and responses to the instruction calls sent to the virtual compute instance.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.

Abstract: Systems, methods, and media for presenting medical imaging data in an interactive virtual environment reality are provided. In some embodiments, a system comprises a head mounted display (HMD) that: determines that a transparent 3D object overlaps a 3D model of a portion of anatomy based on a medical imaging scan; sets values for pixels corresponding to portions of the 3D model not occluded by the transparent object by performing a shading operation; sets values for pixels corresponding to portions of the 3D model at the boundary of the transparent object to intensity values taken from the medical imaging data; displays the 3D model with an exterior surface shaded to evoke a 3D object, and internal surfaces at the boundaries of the transparent object not shaded to preserve details embedded in the medical imaging data.

Abstract: A processor to facilitate acceleration of instruction execution is disclosed. The processor includes a plurality of execution units (EUs), each including an instruction decode unit to decode an instruction into one or more operands and opcode defining an operation to be performed at an accelerator, a register file having a plurality of registers to store the one or more operands and an accelerator having programmable hardware to retrieve the one or more operands from the register file and perform the operation on the one or more operands.

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

Abstract: Apparatus and method for processing virtual graphics processor telemetry data based on quanta.

Abstract: According to the present invention, it is possible to (i) prevent a deterioration in display quality caused by a disagreement between a frame interval of content and an interval for updating drawing, and (ii) carry out update of drawing quickly after receipt of a drawing update request. The drawing control section sets a first drawing period and a drawing update waiting period so that the periods become different in length and a combined length of those periods matches a frame interval of content.

Abstract: The present disclosure relates to methods and apparatus of operation of a GPU. The apparatus can determine a plurality of attributes including one or more vertex attributes and one or more instance attributes. The apparatus can also send the plurality of attributes to at least one processing unit. Additionally, the apparatus can store at least one of the plurality of attributes in a buffer of the at least one processing unit. In some aspects, the at least one of the plurality of attributes can include the one or more instance attributes. The apparatus can also retrieve the at least one of the plurality of attributes from the buffer when the at least one of the plurality of attributes is stored in the buffer. Also, the apparatus can store at least some of the plurality of attributes in a cache of the at least one processing unit.

Abstract: Embodiments provide for a graphics processing apparatus comprising a graphics processing engine configured for tiled memory access. In one embodiment the graphics processing engine is configured to render pixel data to a tile of memory and write to metadata associated with the tile of memory that indicates a data characteristic of the pixel data. The data characteristic of the pixel data includes whether the pixel data is transparent or whether the pixel data is an update of data from a previous frame.

Abstract: A graphics processing unit is operable to execute graphics processing programs comprising sequences of instructions to perform graphics processing operations. The graphics processing unit includes execution processing circuitry operable to execute instructions to perform graphics processing operations and instruction issuing circuitry operable to issue instructions to be executed to the execution processing circuitry. The graphics processing unit also includes energy management circuitry operable to monitor the energy usage by the execution processing circuitry when executing instructions, determine, based on the monitoring of the energy usage, a permitted energy usage range for the execution processing circuitry when executing instructions for a future time period, and control the issuing of instructions to the execution processing circuitry by the instruction issuing circuitry during the future time period based on the permitted energy usage range determined for the future time period.

Abstract: A mechanism is described for facilitating intelligent dispatching and vectorizing at autonomous machines. A method of embodiments, as described herein, includes detecting a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a graphics processor. The method may further include determining a first set of threads of the plurality of threads that are similar to each other or have adjacent surfaces, and physically clustering the first set of threads close together using a first set of adjacent compute blocks.