Abstract: Methods and devices for presenting a virtual reality image may include rendering at least one image frame received from an application for a virtual reality image for display on a display device. The methods and devices may include receiving a selection of one of a plurality of tear thresholds that define conditions for tearing in a displayed image. The methods and devices may include determining whether the rendered frame is received prior to the selected one of the plurality of tear thresholds, wherein the selected one of the plurality of tear thresholds occurs after a frame timing event that corresponds to a deadline for initiating display of a new frame. The methods and device may include communicating the rendered image frame to the display device for presentation on the display device when the rendered frame is received prior to the selected one of the plurality of tear thresholds.

Abstract: Methods and apparatus relating to techniques for a dual path sequential element to reduce toggles in data path are described. In an embodiment, switching logic causes signals for a single data path of a processor to be directed to at least two separate data paths. At least one of the two separate data paths is power gated to reduce signal toggles in the at least one data path. Other embodiments are also disclosed and claimed.

Abstract: A method, device and non-transitory computer-readable storage medium for controlling a frame rate of a mobile terminal are disclosed. The method includes obtaining a rendering frame rate of a target object in a current running scene, the target object including a target application or a target layer, setting a composition frame rate in the current running scene according to the rendering frame rate of the target object, composing rendered images in the current running scene at the composition frame rate, and displaying a composed image.

Abstract: A low power consumption semiconductor device is provided. The semiconductor device includes a decoder, a signal generation circuit, and a display device. The decoder includes an analysis circuit and an arithmetic circuit. The analysis circuit has a function of determining whether to decode the received first image data using the received data. The signal generation circuit has a function of generating a signal including an instruction on whether to decode the first image data in response to the determination of the analysis circuit. The arithmetic circuit has a function of decoding the first image data in response to the signal. The display device has a function of maintaining a second image displayed on the display device in the case where the first image data is not decoded in the arithmetic circuit.

Abstract: An electronic device includes a processor configured to generate a slice update map indicating a location of at least one updated slice having a data change in frame data including a plurality of slices; and a display controller configured to extract frame data of the at least one updated slice from a memory based on the slice update map and transfer the frame data to a display driver.

Abstract: An electronic device includes a housing, a display device exposed through a first part of the housing, a recess formed in a second part of the housing, a receptacle formed in the recess, a plurality of conductive contacts disposed inside the receptacle and including a first contact, a first circuit that supplies and/or receives a current of a first level or larger to and/or from the first contact when an external connector is inserted into the receptacle, a first switching device that electrically connects the first circuit with the first contact or to interrupt a connection between the first circuit and the first contact, a second circuit that detects existence of a foreign object contacting the first contact while the external connector is inserted into the receptacle and a control circuit that controls the first switching device based at least in part on information regarding the detected existence of the foreign object.

Abstract: Methods, systems, and computer-readable media for graphics overlays with virtualized graphics processing are disclosed. A virtual GPU is attached to a virtual compute instance. The virtual compute instance is implemented using a physical compute instance, and the virtual GPU is implemented using a physical GPU accessible to the physical instance over a network. An application is executed on the virtual compute instance. One or more graphics instructions associated with the application are sent to the virtual GPU. The virtual GPU is used to generate graphical output based (at least in part) on execution of the one or more graphics instructions. A graphics overlay comprising one or more additional graphical elements is added to the graphical output based (at least in part) on execution of one or more additional graphics instructions. The one or more additional graphics instructions are not generated by the execution of the application.

Abstract: One or more copy commands are scheduled for locating one or more pages of data in a local memory of a graphics processing unit (GPU) for more efficient access to the pages of data during rendering. A first processing unit that is coupled to a first GPU receives a notification that an access request count has reached a specified threshold. The first processing unit schedules a copy command to copy the first page of data to a first memory circuit of the first GPU from a second memory circuit of the second GPU. The copy command is included within a GPU command stream.

Abstract: An image display device includes: a storing section configured to store associating information that associates information indicating one or more providing sources of image data with each of one or more display areas set within a display screen; an obtaining section configured to obtain image data from a providing source corresponding to each of one or more display areas on the basis of the associating information stored in the storing section; a forming section configured to form display image data of a display image to be displayed on the display screen on the basis of the image data being obtained by said obtaining section for each of one or more display areas; and a display processing section configured to display the display image corresponding to the display image data formed by the forming section on the display screen.

Abstract: A by-divided area reduction ratio calculation unit determines a reduction ratio based on a deformation parameter for image deformation processing for each of a plurality of divided areas constituting an input image. A by-divided area reduction unit reduces, based on the reduction ratio determined for each of the divided areas, an image in the divided area, and stores the reduced image in a storage unit. A deformation unit performs image deformation processing based on the deformation parameter for the reduced image in the divided area stored in the storage unit.

Abstract: An apparatus and method for dynamic provisioning, quality of service, and prioritization in a graphics processor. For example, one embodiment of an apparatus comprises a graphics processing unit (GPU) comprising a plurality of graphics processing resources; slice configuration hardware logic to logically subdivide the graphics processing resources into a plurality of slices; and slice allocation hardware logic to allocate a designated number of slices to each virtual machine (VM) of a plurality of VMs running in a virtualized execution environment, the slice allocation hardware logic to allocate different numbers of slices to different VMs based on graphics processing requirements and/or priorities of each of the VMs.

Abstract: Various techniques for providing a fault-tolerant graphics display engine are disclosed herein. In an example, a machine identifies a buffer under-run at a data buffer (DBUF) of a display engine. The machine adjusts a latency tolerance of the DBUF in response to identifying the buffer under-run. The machine determines that the buffer under-run at the DBUF persists after adjusting the latency tolerance. The machine determines whether a preset correction limit has been reached. If the preset correction limit has not been reached, the machine further adjusts the latency tolerance of the DBUF. If the preset correction limit has been reached, the machine removes, from a visual output associated with the display engine, one or more non-critical display assets.

Abstract: An apparatus includes a plurality of compute nodes and a baseboard management controller that is shared by the plurality of compute nodes to manage video for the compute nodes. The baseboard management controller includes video controllers that are associated with the plurality of compute nodes and at least one resource that is shared by the video controllers.

Abstract: An information handling system includes a host processing system and a management controller. The host processing system includes a main processor that instantiates a management controller agent, a graphics processing unit (GPU), and a GPU throttle module. The management controller accesses the management controller via a first interface to obtain a performance status from the GPU, determine that the performance status is outside of a status threshold, and direct, via a second interface of the information handling system, the GPU throttle module to throttle the GPU to bring the performance status to within the status threshold.

Abstract: A device may allocate one or more frame buffers. In response to a command to open an application after allocating the one or more frame buffers, the device may reassign one or more of the frame buffers to the application. Furthermore, the device may store, based on instructions of the application, content data in the one or more reassigned frame buffers. The device may output, for display on a display screen, content based on the content data in the one or more reassigned frame buffers.

Abstract: A graphics processing system comprises at least one memory device storing a plurality of pixel command threads and a plurality of vertex command threads. An arbiter coupled to the at least one memory device is provided that selects a pixel command thread from the plurality of pixel command threads and a vertex command thread from the plurality of vertex command threads. The arbiter further selects a command thread from the previously selected pixel command thread and the vertex command thread, which command thread is provided to a command processing engine capable of processing pixel command threads and vertex command threads.

Abstract: A mechanism is described for facilitating intelligent dispatching and vectorizing at autonomous machines. A method of embodiments, as described herein, includes detecting a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a graphics processor. The method may further include determining a first set of threads of the plurality of threads that are similar to each other or have adjacent surfaces, and physically clustering the first set of threads close together using a first set of adjacent compute blocks.

Abstract: A technique for graphics processing, which completes graphics processing of an image loaded from a system memory by performing a series of slice processing steps. A device for graphics processing has an internal vector dynamic memory for buffering slices of pixel data loaded from the system memory. The internal vector dynamic memory has a first buffer for buffering non-overlapped pixel data, which is not reused in a next slice processing step and a second buffer for buffering overlapped pixel data, which is reused in the next slice processing step.

Abstract: Examples disclosed herein relate to a computing device. In one aspect, the computing device may include a housing including a first point and a second point spatially separated from each other, a first and second wireless communications modules, and a controller. A first waveguide may couple the first point to an input of the first wireless communications module, where an output of the first wireless communications module may be coupled to an input of the controller. A second waveguide may couple the second point to an output of the second communications module, where an input of the second communications module may be coupled to an output of the controller.

Abstract: A weighed run-length encoding and decoding method and related devices and encoded bitstream. The encoded bitstream can comprise one or more of the following: a skip command packed into a nybble, the skip command indicating how many transparent pixels which are inserted into the bitstream, wherein there is up to a maximum number of transparent pixels; a solid command packed into a nybble, the solid command indicating how many solid pixels should be inserted into the decoded bitstream, wherein there are up to the maximum number of solid pixels; and a quote command packed into a nybble, the quote command indicating how many quoted pixels should be inserted into the decoded bitstream, wherein there are up to the maximum number of quoted pixels.