Patents Examined by Hau Nguyen
  • Patent number: 9183662
    Abstract: One embodiment of the present invention sets forth a technique for specifying scene programs, where the effect of executing a particular scene program is to generate a sequence of graphics commands. The application programming interface is extended to include calls used to specify a high-level scene program. Upon receiving a high-level scene program, the graphics driver generates a machine code scene program. When an application program emits a call to execute one or more machine code scene programs, the graphics driver transmits corresponding scene programs execution commands to the graphics pre-processing unit. For each scene program execution command, the graphics pre-processing unit processes instructions, programmatically reconfigures the graphics pipeline based on the execution of the machine code scene program, and launches one or more parallel threads that execute commands within the graphics pipeline.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: November 10, 2015
    Assignee: NVIDIA Corporation
    Inventors: Jason Sams, Cass W. Everitt, Mark J. Kilgard
  • Patent number: 9183615
    Abstract: A display device includes a driver connected to a display panel and transmitting scan signals or data signals to the display panel, a frame memory connected to the driver, storing image data and transmitting at least some of the image data to the driver, and a controller connected to the driver and the frame memory, generating a control signal and transmitting the control signal to the driver or the frame memory, wherein each of the sub-fields includes an address period in which the scan signals are transmitted to the respective pixel rows, the controller transmits the control signal to the driver to transmit the scan signals to the pixel rows during a current frame such that the scan signals corresponding to the current frame are transmitted after, among the image data corresponding to the current frame, the image data corresponding to the pixel rows are stored in the frame memory.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 10, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji Gong Lee, Sang Jin Pak, Hideo Yoshimura, Sang Kwon Ha
  • Patent number: 9183152
    Abstract: Before initializing a memory of an information handling system, a method includes loading an image of a video option ROM code for a graphics interface device to a cache associated with a processor of the information handling system, and executing the video option ROM code to initialize the graphics interface device. The method also includes executing a memory reference code to initialize the memory, and while executing the memory reference code, providing status information from the graphics interface device.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: November 10, 2015
    Assignee: Dell Products, LLP
    Inventors: Bi-Chong Wang, Austin P. Bolen, Madhusudhan Rangarajan
  • Patent number: 9183613
    Abstract: Apparatuses, methods and storage medium associated with operating an application are disclosed herein. In embodiments, a method may include locally creating on a client computing device, by a client side of the application, a graphics context of the application. The graphics context may include a plurality of rendering resources associated with generating display frames of the application. The client side of the application may cause creation of a copy of the graphics context, by a remote side of the application, on a collection of remote computing resources. The client side of the application may then adaptively cause generation of a display frame locally or remotely. Other embodiments may be described and claimed.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: November 10, 2015
    Assignee: Intel Corporation
    Inventors: Zhipeng Gong, Jianyu Li
  • Patent number: 9177353
    Abstract: A protected graphics module can send its output to a display engine securely. Secure communications with the display can provide a level of confidentiality of content generated by protected graphics modules against software and hardware attacks.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 3, 2015
    Assignee: Intel Corporation
    Inventors: Siddhartha Chhabra, Uday R. Savagaonkar, Prashant Dewan, Michael A. Goldsmith, David M. Durham
  • Patent number: 9153053
    Abstract: Systems, apparatus, methods and computer program products are described below for rendering a graphical user interface by selectively compositing display contents. In general for each of one or more content producers, where each content producer is associated with content storage containing display content, display content for output is identified depending on the content consumer to which the graphical user interface is being rendered.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: October 6, 2015
    Assignee: Apple Inc.
    Inventor: Michael James Paquette
  • Patent number: 9152372
    Abstract: A method and system for enabling multiple video graphics array (VGA) cards to process image data are disclosed. Specifically, one embodiment of a graphics system includes a first video graphics array (VGA) card having a first and a second connection ports, a second VGA card having a first and a second connection ports, a third VGA card having a first and a second connection ports, and a connecting device for electronically connecting the first, the second, and the third VGA cards via connections that transfer data. The connecting device is further configured to connect the first connection port of the first VGA card to either the first or the second connection port of the second VGA card and connect the second connection port of the first VGA card to either the first or the second connection port of the third VGA card.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: October 6, 2015
    Assignee: NVIDIA CORPORATION
    Inventor: Tiecheng Liang
  • Patent number: 9147225
    Abstract: A graphics processing unit (GPU) and a management method of the GPU are provided. The GPU includes at least one graphics engine and an engine manager. The graphics engine performs a video decoding function or a graphics rendering function according to a graphics command from a driver software. The engine manager records a workload index of each graphics engine. The engine manager also adjusts the work ability of one of or more of the at least one graphics engine according to an adjustment command from the driver software. The driver software provides the adjustment command according to the workload index.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: September 29, 2015
    Assignee: VIA Technologies, Inc.
    Inventors: Ping-Huei Hsieh, Yi-An Chen
  • Patent number: 9147224
    Abstract: One embodiment of the present invention sets forth a technique for receiving versions of state objects at one or more stages in a processing pipeline. The method includes receiving a first version of a state object at a first stage in the processing pipeline, determining that the first version of the state object is relevant to the first stage, incrementing a first reference counter associated with the first version of the state object, assigning the first version of the state object to work requests that arrive at the first stage subsequent to the receipt of the first version of the state object, and transmitting the first version of the state object to a second stage in the processing pipeline.
    Type: Grant
    Filed: November 11, 2011
    Date of Patent: September 29, 2015
    Assignee: NVIDIA Corporation
    Inventors: Sean J. Treichler, Lacky V. Shah, Daniel Elliot Wexler
  • Patent number: 9141170
    Abstract: Techniques are described to monitor a level of graphics processing activity and control power usage based on the level. When no graphics processing activity is detected for a period of time, then a timing controller for a display device is instructed to capture a current image and repeatedly display the captured image. The graphics processing devices can be powered down. When graphics processing activity is detected, the graphics processing devices are powered up and the components used to capture an image and display the captured image are powered down.
    Type: Grant
    Filed: December 31, 2013
    Date of Patent: September 22, 2015
    Assignee: Intel Corporation
    Inventors: Seh W. Kwa, Michael Calyer, Ravi Ranganathan, Narayan Biswal
  • Patent number: 9142002
    Abstract: A graphic processor device is implemented on a field programmable gate array (“FPGA”) circuitry comprises a pipeline formatter that sets graphic commands and vertex data into structures, and a rasterizer that interpolates between vertices in the vertex data to generate lines and filling between at least one edge to generate a structure, wherein output of the rasterizer is a stream of fragments that become pixels. The graphic processor device further includes a frame buffer that receives a stream of fragments and blends a plurality of fragments before the plurality of fragments are stored in a frame buffer, and an output processor configured to retrieve a plurality of fragments from the frame buffer and transmits a plurality of pixels according to a predefined resolution.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: September 22, 2015
    Assignee: L-3 COMMUNICATIONS CORPORATION
    Inventor: Marcus Franklin Dutton
  • Patent number: 9142183
    Abstract: The display management system includes an operation display apparatus, a master display apparatus, and a management server. The management server has a selection unit that causes the user to select image processing that is executed by the master display apparatus when the image edited by the user by using the operation display apparatus is checked using the master display apparatus, and an instruction unit that instructs the operation display apparatus to execute the image processing selected by the selection unit in a case where this image processing can be executed by the operation display apparatus. The operation display apparatus has an image processing unit that subjects the inputted image to the image processing performed under instruction by the instruction unit and a display unit that displays on a display unit the image subjected to the image processing by the image processing unit.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: September 22, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventor: Satoshi Kirihara
  • Patent number: 9142004
    Abstract: Methods, techniques, and systems for dynamically allocating graphics processing units among virtual machines are provided. Example embodiments provide a dynamic GPU allocation system (“DGAS”), which enables the efficient allocation of physical GPU resources to one or more virtual machines. In one embodiment, the DGAS comprises virtualization logic running on a server computing system that computes GPU benefit factors for the virtual machines on a dynamic basis, and combines the computed GBFs with static priorities to determine a ranked ordering of virtual machines. The available GPU resources are then allocated to some subset of these ranked virtual machines as physical GPU capacity is matched with the requirements of the subset. Physical GPU resources are then allocated to the subset of virtual machines that have the highest promise of GPU utilization.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: September 22, 2015
    Assignee: VMware, Inc.
    Inventors: Salim Abiezzi, Jose Fonseca, Mark Sheldon, Alan Hourihane
  • Patent number: 9135672
    Abstract: A display system and a data transmission method thereof are provided. When a first frame stored in a frame buffer is identical to a second frame to be output from an audio and video (AV) source, the AV source is set an AV control signal corresponding to a self-refresh mode, and a timing controller reads the first frame to output a display data controlled by the AV control signal. When the first frame is differed from the second frame, the AV source is set the AV control signal corresponding to a data update mode and a AV data signal corresponding to the second frame, and the timing controller stores the second frame in the frame buffer controlled by the AV control signal and outputs the display data corresponding to the first frame or the second frame according the timing sequences of the AV data signal and the display data.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: September 15, 2015
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventors: Chi-Cheng Chiang, Chih-Hsuan Wang
  • Patent number: 9129344
    Abstract: A method and system for padding an array of data on-the-fly in a direct memory access (DMA) controller. The method includes receiving the array of data in the DMA controller. The method also includes identifying edge groups of pixels at edges of the array of data and creating a padded region of data words along a periphery of the array of data. Each data word includes pixels of a corresponding edge group. The data words are then stored in a memory along with received array of data. Further, the method includes sending a request for padded data at a location in the memory, the padded data defining the array of data and the padded region of data words. Further, the method also includes translating the location of the padded data to addresses of one of, the data words and the array of data in the memory and retrieving the padded data at the addresses in the memory.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: September 8, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Niraj Nandan, Sivakumar Ramaiyan
  • Patent number: 9129394
    Abstract: Embodiments described herein relate to improving throughput of a CPU and a GPU working in conjunction to render graphics. Time frames for executing CPU and GPU work units are synchronized with a refresh rate of a display. Pending CPU work is performed when a time frame starts (a vsync occurs). When a prior GPU work unit is still executing on the GPU, then a parallel mode is entered. In the parallel mode, some GPU work and some CPU work is performed concurrently. When the parallel mode is exited, for example when there is no CPU work to perform, the parallel mode may be exited.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: September 8, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Oreste Dorin Ungureanu, Harneet Sidhana, Mohamed Sadek, Sandeep Prabhakar, Steve Pronovost
  • Patent number: 9122632
    Abstract: Methods and apparatus relating to programmable power performance optimization for graphics cores are described. In one embodiment, the first frame of a scene is analyzed. It is then determined whether to optimize one or more operations, to be performed on one or more frames of the scene, based on the second frame of the scene and an idle status of one or more subsystems of a processor. And, one or more optimization operations are performed on a third frame of the scene based on the determination of whether to optimize the one or more operations. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 30, 2012
    Date of Patent: September 1, 2015
    Assignee: Intel Corporation
    Inventor: Linda L. Hurd
  • Patent number: 9117284
    Abstract: An asynchronous computing and rendering system includes a data storage unit that provides storage for processing a large-scale data set organized in accordance to data subregions and a computing cluster containing a parallel plurality of asynchronous computing machines that provide compute results based on the data subregions. The asynchronous computing and rendering system also includes a rendering cluster containing a parallel multiplicity of asynchronous rendering machines coupled to the asynchronous computing machines, wherein each rendering machine renders a subset of the data subregions. Additionally, the asynchronous computing and rendering system includes a data interpretation platform coupled to the asynchronous rendering machines that provides user interaction and rendered viewing capabilities for the large-scale data set. An asynchronous computing and rendering method is also provided.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: August 25, 2015
    Assignee: NVIDIA CORPORATION
    Inventors: Marc Nienhaus, Joerg Mensmann, Hitoshi Yamauchi
  • Patent number: 9117285
    Abstract: A system for processing a plurality of graphical programs on a centralized computer system whereby the images produced by the programs are compressed and transmitted to a plurality of remote processing devices where they are decompressed. Compression assistance data (CAD) is produced by intercepting instructions outputted by the programs and the CAD is then used in the compression step.
    Type: Grant
    Filed: December 21, 2013
    Date of Patent: August 25, 2015
    Assignee: T5 LABS LTD
    Inventors: Graham Clemie, Dedrick Duckett
  • Patent number: 9116697
    Abstract: Techniques are described to monitor a level of graphics processing activity and control power usage based on the level. When no graphics processing activity is detected for a period of time, then a timing controller for a display device is instructed to capture a current image and repeatedly display the captured image. The graphics processing devices can be powered down. When graphics processing activity is detected, the graphics processing devices are powered up and the components used to capture an image and display the captured image are powered down.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: August 25, 2015
    Assignee: Intel Corporation
    Inventors: Seh W. Kwa, Michael Calyer, Ravi Ranganathan, Narayan Biswal