Abstract: Provided is a method for scheduling operations called by a task on a real-time or non-real-time processor. Execution durations are provided for operations. A call is received from a task for an operation. A determination is made of a latency requirement for a first processor and of the execution duration of the called operation. The called operation is executed on the first processor in response to determining that the determined execution duration is less than the latency requirement. The called operation is executed on a second processor in response to determining that the determined execution duration is greater than the latency requirement.
Type:
Grant
Filed:
September 8, 2005
Date of Patent:
June 8, 2010
Assignee:
International Business Machines Corporation
Abstract: A data transfer control device includes an ATA device-side I/F which transfers data between the data transfer control device and an ATA host through a bus ATABUS1, an ATA host-side I/F which transfers data between the data transfer control device and an ATA device through a bus ATABUS2, a first interface which transfers data through a first bus, and a transfer controller which controls data transfer among the device-side I/F, the host-side I/F, and the first interface.
Abstract: A multiple protocol address register method between a communication terminal and the register server includes transmitting a first register request for requesting to register a first protocol address from the communication terminal to the register server; storing the first protocol address and the identification to the register server; transmitting a response to the first register request from the register server to the communication terminal together with a first communication rule; transmitting the second register request from the communication terminal to the register server on the basis of the first communication rule; storing, when the second register request is created based on the first communication rule, the second protocol address in the register server; and transmitting a response to the second register request from the register server to the communication terminal.
Abstract: A data transfer interface system is provided that directly transfers data from one data storage drive to another data storage drive under the control of a host. The host and data storage drives are jointly connected to one another with data lines and control lines. Each data storage drive is connected separately to the host with a read/write command line. The host initializes the data storage drives providing initialization data to the drives where the data may include position information and commend information. After initialization, the host concurrently instructs one data storage drive to read the data from the drive while the other data storage drive writes the data to memory.
Abstract: The disclosed technology can be used to develop systems and perform methods that receive and process I/O requests directed to at least a part of a logical unit of storage. The I/O requests can be associated with different times corresponding to when such I/O requests were received. Nodes that include non-overlapping address ranges associated with the logical unit of storage can be formed in response to receiving the I/O requests and such nodes can be subsequently organized into a tree data structure. The tree data structure can serve as a basis for determining address overlap, for example to enable processing a first operation associated with a first one of the I/O requests in accordance with the first I/O request's receipt time, while one or more other operations associated with a different I/O request may be processed irrespective of that different I/O request's receipt time.
Abstract: Transferring data elements from a source to a destination includes providing a transmission queue at the source, where data elements in the transmission queue are transferred from the source to the destination, determining an optimal length for the transmission queue, where the optimal queue length is inversely proportional data latency time at the destination, and, if the optimal length is greater than an instantaneous length of the transmission queue, adding data elements to the transmission queue. Adding data elements may include adding a number of elements corresponding to a difference between the optimal length and the instantaneous length of the transmission queue. Determining optimal length may include dividing a constant by the data latency time at the destination. Transferring data elements may also include providing a network between the source and the destination.
Type:
Grant
Filed:
August 24, 2004
Date of Patent:
June 1, 2010
Assignee:
EMC Corporation
Inventors:
Alexandr Veprinsky, Anestis Panidis, Ramprasad Shetty, Ilya E. Garelik, Mark J. Halstead, Sergey Kornfeld
Abstract: A system includes an information processing apparatus and a peripheral which are connected to each other. Initially, the information processing apparatus transmits, to the peripheral, a request to use a service provided by the peripheral. The peripheral determines whether to grant use permission to the received request, and notifies the information processing apparatus which has transmitted the request of the determination result. The peripheral stores information associated with the information processing apparatus to which use permission is granted in response to the request. The information processing apparatus then receives, from the peripheral, a response to the request.
Abstract: A network controller with a bootable Host Bus Adapter, particularly suitable for iSCSI applications is described. In one example, this includes, a host bus interface, a register to the host bus indicating a mass storage device, a network interface, and a boot memory extension including a driver for the mass storage device that binds to a BIOS.
Abstract: A cellular phone. The cellular phone comprises a connector, a first memory module, a second memory module, and a controller. The connector is used for physically connecting the cellular phone to an external device. The first memory module stores phone data. The second memory module stores application data received from the external device. The controller determines whether the connector is connected to the external device. If the connector is not connected to the external device, access right of both the first and second memory modules is granted exclusively to the cellular phone. If the connector is connected to the external device, access right of the first memory is granted exclusively to the cellular phone, and access right of the second memory module is granted exclusively to the external device.
Abstract: A method for defining a cycle time for a transmission cycle on a system bus of a monitoring and/or control system having at least one communication module and at least one input/output module, which is connected to the communication module via the system bus for transmitting measurement and/or control signals and is intended to input and/or output measurement and/or control signals to field applications, the at least one communication module having a time control unit for controlling a transmission cycle which is constantly repeatedly carried out and has defined communication times for the communication and input/output modules which are connected to the system bus, comprises measuring the signal propagation times on the system bus and defining the cycle time for a transmission cycle on the system bus on the basis of the longest signal propagation time measured.
Abstract: An apparatus and method is provided to facilitate Input/Output (I/O) transfer in resource limited storage environment. Scatter gather list, segment and memory data buffer allocation are dynamically managed. I/O transfer performance is increased through the use of a data cut-through buffer mechanism.
Type:
Grant
Filed:
June 23, 2006
Date of Patent:
June 1, 2010
Assignee:
Intel Corporation
Inventors:
Naichih Chang, Pak-Lung Seto, Victor Lau
Abstract: A method comprises providing a free buffer pool in a memory including a non-negative number of free buffers that are not allocated to a queue for buffering data. A request is received to add one of the free buffers to the queue. One of the free buffers is allocated to the queue in response to the request, if the queue has fewer than a first predetermined number of buffers associated with a session type of the queue. One of the free buffers is allocated to the queue, if a number of buffers in the queue is at least as large as the first predetermined number and less than a second predetermined number associated with the session type, and the number of free buffers is greater than zero.
Type:
Grant
Filed:
October 6, 2006
Date of Patent:
June 1, 2010
Assignee:
Agere System Inc.
Inventors:
Ambalavanar Arulambalam, Jian-Guo Chen, Nevin C. Heintze, Qian Gao Xu, Jun Chao Zhao
Abstract: Communicating via a network using a universal network driver interface is disclosed. It is determined whether a universal network device interface (UNDI) driver is installed. A UNDI driver is scanned for if it is determined that no UNDI driver is installed. In the event a UNDI driver is found, a PCI network device that is associated with the UNDI driver is scanned for. If a PCI network device associated with the UNDI driver is found, the UNDI driver is loaded and initialized for the PCI network device.
Abstract: Provided is an information system for preserving data of a storage device in a computer that repeats the connection to and disconnection from a communication network. The computer acquires data to be written into the storage device and manages the update status of the storage device, transfers the data written into the storage device to the storage controller independent from the writing of data into the storage device when the computer is in a communicable state with the storage controller, and discontinues the transfer of data written into the storage device to the storage controller and manages the transfer status when the computer is not in a communicable state with the storage controller.
Abstract: Device images, for example IDE mass storage device images, may be enabled and disabled without disrupting a host system. In one embodiment, the invention includes a memory device register to indicate the presence of a memory device to a computer system, a switch coupled to the memory device register to set the memory device register to indicate the presence of a memory device, and an external interface coupled to the switch to operate the switch.
Abstract: A data processing apparatus transmits and receives moving image data to and from an external device through a transmission path. A first pipe used for transferring the moving image data and a second pipe used for transferring timing information relating to the processing timing of the moving image data are provided on the transmission path. The moving image data is being transferred to the external device through the first pipe in parallel with the timing information relating to the moving image data being transferred through to the external device through the second pipe.
Abstract: A system for installing an electronic device connected to a host device with consideration given to the host controller that enables the connection mechanism is provided. Information about the electronic device and the host controller is determined. An identifier that identifies the electronic device and the host controller is created based on the determined information. The identifier is used to search for a device driver for the electronic device that is specific to the host controller.
Type:
Grant
Filed:
February 27, 2006
Date of Patent:
May 25, 2010
Assignee:
Microsoft Corporation
Inventors:
Vatsal Bhardwaj, Joby S. Lafky, Sanford L. Spinrad
Abstract: A data processing system includes at least a first processing node having an input/output (I/O) controller and a second processing including a memory controller for a memory. The memory controller receives, in order, pipelined first and second DMA write operations from the I/O controller, where the first and second DMA write operations target first and second addresses, respectively. In response to the second DMA write operation, the memory controller establishes a state of a domain indicator associated with the second address to indicate an operation scope including the first processing node. In response to the memory controller receiving a data access request specifying the second address and having a scope excluding the first processing node, the memory controller forces the data access request to be reissued with a scope including the first processing node based upon the state of the domain indicator associated with the second address.
Type:
Grant
Filed:
September 15, 2005
Date of Patent:
May 25, 2010
Assignee:
International Business Machines Corporation
Inventors:
George W. Daly, Jr., James S. Fields, Jr., Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli
Abstract: A storage system having a storage device in communication with a host and including one or more function devices for communicating with application software modules, in accordance with an embodiment of the present invention. Said application software modules issuing vendor specific commands to access said function devices, said function devices remaining unknown to said host and recognizing said vendor specific commands for acting thereupon, wherein said storage device causing said application software modules to access said function devices to increase the security of said storage device.
Abstract: A computing system having a plurality of processors including a first processor configured with an address port and a second processor configured with an address port, and a memory device having a first port configured as an address port and to alternatively interface with the address port of the first processor and the address port of the second processor.