Abstract: Deselect times can be specified for transactions that are to utilize a communication bus shared by multiple devices. A host can communicate with a multiplexer to select a channel for communication on that bus. If this host communicates with the multiplexer over the bus as well, the host can be prevented from instructing the multiplexer to deselect a channel if the bus is hung. To provide for recovery in such situations, one or more deselect times can be specified for one or more channels of a bus. If a transaction for a device on one of these channels is ongoing when the deselect time is reached, the multiplexer can automatically deselect that channel in order to enable other devices to communicate over other channels on that bus. In some embodiments, a riskiness of a transaction or device can be determined for purposes of applying or determining a relevant deselect time.

Abstract: A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, from a driver of the host system, a request regarding a page of data stored in the second memory; responsive to the request, transfer the page from the second memory to a buffer; and write the page from the buffer to the first memory, wherein the page is written to the first memory during at least one of a second plurality of windows corresponding to a refresh timing for the memory bus, and the refresh timing is controlled at the host system.

Abstract: Systems, methods and computer software are disclosed for fronthaul. In one embodiment a method is disclosed, comprising: providing a virtual Radio Access Network (vRAN) having a centralized unit (CU) and a distributed unit (DU); and interconnecting the CU and DU over an Input/Output (I/O) bus using Peripheral Component Interconnect-Express (PCIe); wherein the CU and the DU include a PCI to optical converter and an optical to PCI converter.

Abstract: Systems involving distributed control functions are described herein. Each member or device within the system has responsibility for controlling part of the system's behavior, and includes logic to determine what action, if any, will follow as a response to determining information or receiving information from other members or devices within the system. A change of status of one member of a system may provide a basis for action by another member of the system. Status may be the result of sensing a condition of the environment, sensing the condition of a component, receiving the output of a conventional sensor, and/or sensing the condition of a link between components. In some embodiments, action taken by a member of the system may include collecting data during law enforcement activities.

Abstract: A mother board topology including a processor operable to be coupled to one or more communication channels for communicating commands. The topology includes a first communication channel electrically coupling a first set of two or more dual in-line memory modules (DIMMs) and a first primary data buffer on a mother board. The topology includes a second communication channel electrically coupling a second set of two or more DIMMs and a second primary data buffer on the mother board. The topology includes a third channel electrically coupling the first primary data buffer, the primary second data buffer, and the processor.

Abstract: A slave device includes: a serial communications slave having an address designated for performing serial communications with a master; a single address determination pin configured to be, selectively, connected to a power terminal without being connected to a first external resistor, connected to a ground terminal without being connected through a second external resistor, connected to the power terminal through the first external resistor, or connected to the ground terminal through a second external resistor; and an address allocator configured to designate the address of the serial communications slave based on a plurality of state bits determined depending on a connection state of the single address determination pin.

Abstract: A hybrid management cable includes a cable connector having a first cable sub-connector and a second cable sub-connector, The cable connector connects to a hybrid management switch connector on a hybrid management switch and, in response, engages the first cable sub-connector with a first hybrid management switch sub-connector on the hybrid management switch connector, and engages the second cable sub-connector with a second hybrid management switch sub-connector on the hybrid management switch connector. A cable conduit extends from the cable connector. A first management data transmission medium is connected to the first cable sub-connector, located in the cable conduit, and extends along the length of the cable conduit. A second management data transmission medium is connected to the second cable sub-connector, located in the cable conduit and isolated from the first management data transmission medium, and extends along the length of the cable conduit.

Abstract: An apparatus includes a bi-phase mark coded (BMC) input port configured to receive BMC signals from a universal serial bus (USB) cable. The apparatus further includes a threshold adjustment circuit configured to generate a threshold, and a comparator configured to compare an input BMC signal from the BMC input port and the threshold and based on the comparison, generate an adjusted input BMC signal. The threshold adjustment circuit is further configured to adjust the threshold based upon the input BMC signal.

Abstract: The present invention relates to a data processing method, including the steps of intercepting a signal within a communications channel between a predefined peripheral device for a computing system and an application executing on the computing system and processing the signal and performing one or more actions in response to the processing. At least one action affects onward transmission of one or more signals within the communications channel. A data processing system is also described.

Abstract: A communication method for a fan includes transmitting an initial signal with a specific duty cycle pattern to the fan; entering a communication mode after the fan receives the initial signal; reading information of the fan by a firmware of the fan; and transforming the information of the fan into a fake tachometer (TACH) signal and transmitting the fake TACH signal to a controller via a TACH signal line under the communication mode.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device determines a number storage units that have been provisioned on the storage network but has not been assigned for storage of data. The computing device then determines a storage utilization level for each of a plurality of active storage units associated with the storage network and based on the storage utilization level, determines whether to activate one or more inactive storage units. The computing device is configured to determine at least a portion of the number of inactive storage units for activation and issue an assignment message to the at least a portion of the number of inactive storage units.

Abstract: A communication apparatus is disclosed with a communication controller that has a host-side communication interface for communicating with a host and a plurality of slave-side communication interfaces. Each slave-side communication interface has a plurality of electrical pins that are configurable to define a communication port that implements a selected communication protocol thereon. Each pin is in electrical communication with a slave socket having a predetermined layout. Each slave socket is configured to receive a protocol adapter that corresponds to the selected communication protocol and that is configured to facilitate communication between an external slave device and the relevant communication port.

Abstract: An example method comprises establishing, via a first data communication interface of a first computing device, a physical connection to between the first computing device and a second computing device. The method also includes receiving, at the first computing device, input data via a second data communication interface of the first computing device. The method further includes controlling an operation at the first computing device based on the input data when the input data is received prior to establishing the connection. The method further includes routing the input data to the second computing device via an input data switch of the first computing device when the input data is received after establishing the connection.

Abstract: A device may include a plurality of first communication interfaces configured to communicate with a plurality of external client devices, a second communication interface configured to communicate with an external master device, a third communication interface configured to communicate with an external first device, and a first controller. The second communication interface may perform a one-to-many communication with the plurality of first communication interfaces over a first protocol. The third communication interface may communicate with the plurality of first communication interfaces or the second communication interface via the first controller over a second protocol that is different from the first protocol.

Abstract: An ultraconverged architecture has multiple availability zones within a single server. The functionality in each of the availability zones is independently controlled, such that resetting and/or disconnecting any component in any availability zone from power and replacing said component does not affect availability of any other component in any other availability zone. A manager of availability zones controls reset functionality in each of a plurality of availability zones. The manager of availability zones generates a requested reset type in the requested availability zone. The manager of availability zones generates reset signals or requests for some or all components located in multiple availability zones. The reset signal or request is generated upon external request to the manager of availability zones that specifies the reset type, the availability zone, and optionally the list of components to be reset. The manager of availability zones discovers and enumerates the components in each availability zone.

Abstract: Embodiments herein describe techniques for separating data transmitted between I/O functions in an integrated component and a host into separate data paths. In one embodiment, data packets are transmitted using a direct data path that bypasses a switch in the integrated component. In contrast, configuration packets (e.g., hot-swap, hot-add, hot-remove data, some types of descriptors, etc.) are transmitted to the switch which then forwards the configuration packets to their destination. The direct path for the data packets does not rely on switch connectivity (and its accompanying latency) to transport bandwidth sensitive traffic between the host and the I/O functions, and instead avoids (e.g., bypasses) the bandwidth, resource, store/forward, and latency properties of the switch. Meanwhile, the software compatibility attributes, such as hot plug attributes (which are not latency or bandwidth sensitive), continue to be supported by using the switch to provide a configuration data path.

Abstract: An apparatus may include a serial data output port configured to send output data to a electronic device. The apparatus may include a serial data input port configured to receive input data from another electronic device. The apparatus may include a chip select output port configured to send output to the electronic devices connected in a daisy chain. The apparatus may include a interface circuit, configured to determine that a given electronic device is to selectively execute a first command. The interface circuit may be further configured to issue a complex command to the electronic devices connected. The complex command may indicate to the f electronic devices that additional commands are to be selectively executed.

Abstract: A virus detection system uses a USB relay device that can support not only the use of USB mass storage but also the use of other USB devices such as a mouse. The USB relay device has a connection switching unit for switching a connection state between a first connector unit to which a USB client is connected and a second connector unit connected to a USB host controller. The virus detection system includes a virus check engine unit that performs a virus check of a file acquired from the USB client or the USB host controller via the USB relay device. On the basis of a result of the check by the virus check engine unit, the USB relay device performs switching control of the connection state by the connection switching unit.

Abstract: In one example in accordance with the present disclosure, a modular computing component is described. The modular computing component includes a first terminal to connect the modular computing component to at least one of a host computing device and another modular computing component. Controller memory of the modular computing component stores information relating to at least one of build level information, revision level information, and generation level information. A controller of the modular computing component transmits the at least one of build level information, revision level information, and generation level information to the host computing device.

Abstract: An input/output store instruction is handled. A data processing system includes a system nest coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to at least one external device which is coupled to the at least one input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed. The asynchronous core-nest interface includes an input/output status array with multiple input/output status buffers.