Abstract: Disclosed are systems, computer-readable mediums, and methods for managing input/output operations within a system including at least one client and a storage system. A processor receives information regarding allocated input-output operations (IOPS) associated with a client accessing a storage system storing client data. The information includes a number of allocated total IOPS, a number of allocated read IOPS, and a number of allocated write IOPS. The processor also receives a requested number of write IOPS associated with the at least one client's request to write to the storage system. The processor determines a target write IOPS based on the number of allocated total IOPS, the number of allocated write IOPS and the requested number of write IOPS, and executes the determined target write IOPS within the first time period.

Abstract: In accordance with some embodiments, an apparatus for privacy protection is provided. In some embodiments, the apparatus includes a first device including a receiver configured to receive audio signals, a memory configured to store one or more criteria, and a processor configured to process the received audio signals based on the stored criteria in the memory. The apparatus further includes a second device in communication with the first device, wherein the first device, upon detecting one or more audio sound patterns, is configured to send a notification to the second device.

Abstract: Devices in an array of devices, coupled to a common SPI bus, are automatically assigned identifiers by an enumeration process. In some embodiments, the devices are coupled together in an enumeration daisy chain. The enumeration function is initiated, e.g., by a controller, with a single SPI transaction.

Abstract: A method is performed to compile input data including a plurality of pulse sequences, hardware parameters obtained from a computing device, and a mathematical model with time-dependent control parameters to decrease a computation time of the input data. The method also includes providing the input data to the computing device to allow the computing device to run a computation of the input data. The method further includes converting the pulse sequences into memory-aligned arrays to decrease the computation time of the input data. The method includes calculating optimized output data using an adaptive step size computation to decrease the computation time needed to compute the output data.

Abstract: A USB switching circuit includes a first multiplexer, a second multiplexer coupled with the first multiplexer through transmission paths, and a voltage regulation circuit coupled with the first and second multiplexers. The first multiplexer distributes first data signals to the transmission paths according to first control signals. The second multiplexer distributes a second data signal to the transmission paths according to second control signals. The voltage regulation circuit sets a maximum voltage and a minimum voltage of the first data signals to corresponding to a common voltage. The maximum voltage of the first data signals is not higher than a maximum voltage of the second control signals, or the minimum voltage of the first data signals is not lower than a minimum voltage of the second control signals. The first data signals and the second data signal are generated according to different communication protocols.

Abstract: According to implementations of the subject matter described herein, there is proposed a solution for supporting communications for an FPGA device. In an implementation, the FPGA device includes an application module and protocol stack modules. The protocol stack modules are operable to access target devices based on different communication protocols via a physical interface. The FPGA device further includes a universal access module operable to receive, from the application module, first data and a first identity of a first target device, the first target device acting as a destination of the first data, and transmit, based on the first identity and predetermined first routing information, the first data to a first protocol stack module accessible to the first target device via the physical interface. By introducing the universal access module, it is possible to provide unified and direct communications for the application module.

Abstract: An information handling system includes a processor that provides a USB-2 channel and a USB-3 channel to a device. The device provides the USB-2 and -3 channels to selected ports. Each port includes a USB-3 enable setting. When the USB-3 enable setting for each particular USB port is in a first state, the associated device USB-3 channel is active, and when the USB-3 enable setting for each particular USB port is in a second state, the associated device USB-3 channel is inactive. The USB-3 enable setting for at least one of the USB ports is placed into the second state to reduce electromagnetic interference between the associated USB-3 channel and an antenna.

Abstract: A system includes a storage device; a storage device controller; a first interface configured to connect the storage device controller to the storage device; and a second interface configured to connect the storage device controller to a host device, wherein the storage device is configured to operate in a first mode or a second mode based on a status of a signal at the second interface based on instructions received from the host device.

Abstract: Apparatuses, methods, and computer-readable media are provided for operating a port manager to detect a first link condition or a second link condition of a circuitry. Under the first link condition, a first link between a downstream port of the circuitry and an upstream port of a switch is compatible to a first protocol, and a second link between a downstream port of the switch and an upstream port of a device is compatible to the second protocol. Under the second link condition, the first link exists and is compatible to the first protocol, while there is no second link being compatible to the second protocol. The port manager is to operate the downstream port of the circuitry according to the second protocol on detection of the first link condition, or according to the first protocol on detection of the second link condition. Other embodiments may be described and/or claimed.

Abstract: The invention provides a system capable of remotely controlling electronic apparatus, which includes a cloud management platform and at least one electronic apparatus. The electronic apparatus includes at least one operation element, and a data storage device having a network communication function. The data storage device includes a first transmission interface, a second transmission interface, a data storage unit, and an operation management unit. Via the first transmission interface, data stored in the data storage unit can be read or data can be written into the data storage unit. The operation management unit of the data storage device transmits a specific operation instruction to the operation element via the second transmission interface after receiving the specific operation instruction sent from the cloud management platform, such that the operation element can execute a corresponding operation according to the specific operation instruction.

Abstract: Software bus bridges (410.xy) are ordered in an order of associated bus identifiers (B), to allow programs accessing the corresponding physical bridges (310.xy) to find the correct software bus bridge either based on the bus identifiers, in which case the particular ordering of software bridges is unimportant, or based on the order of the software bridges. In some cases, this facilitates software porting across platforms with similar programmatic interfaces to the physical bridges but with different bus identifier ranges associated with physical bridges or with programmatic interfaces. A procedure is provided for determining the correct software bridge from a bus identifier. Other embodiments are also provided.

Abstract: A first solid state drive (SSD) includes a first built-in network interface device configured to communicate via a network fabric, and a second SSD includes a second built-in network interface device configured to communicate via the network fabric. A connection is opened between the first SSD and the second SSD over the network fabric. Based on a non-volatile memory over fabric (NVMe-oF) communication protocol, an NVMe command to transfer data between the first SSD and the second SSD over the connection is encapsulated in a capsule. The capsule is sent from the first SSD to the second SSD over the connection via the network fabric. The second SSD executes the NVMe command in the capsule to transfer the data between the first SSD and the second SSD over the connection.

Abstract: In an embodiment, a method for writing to a set of serial peripheral interface (SPI) slaves coupled to an SPI bus includes: disabling master in slave out (MISO) drivers of the set of SPI slaves using the SPI bus; after disabling the MISO drivers, setting respective slave selection terminals of the set of SPI slaves to an active state; and after setting the respective slave selection terminals of the set of SPI slaves to the active state, simultaneously writing data to the set of SPI slaves using a master out slave in (MOSI) line.

Abstract: A proxy device may change compression of data for a set of local devices. The proxy device may receive compressed data from a remote device, generate first transformed data based on reduction of compression of the compressed data, and transmit the first transformed data to one or more local devices. The proxy device may receive data from a local device, generate second transformed data based on increase in compression of the data, and transmit the second transformed data to the remote device.

Abstract: The present invention relates to the technical field of electronic communication, and specifically disclosed thereby are a master-slave configuration communication protocol, a method for improving compatibility and an electronic device. The master-slave configuration communication protocol comprises: electrically connecting one GPIO pin of a master configuration to at least one kind of slave configuration; the master configuration sending a mock address to the slave configuration through the GPIO pin; and the slave configuration receiving the mock address and comparing the mock address with its native address, if the mock address matches the native address, the slave configuration sends its parameter information to the master configuration.

Abstract: A host system is connected to the internal fabric of a storage system without an intervening external network or director or other component of the storage system controlling the host system's access to the internal fabric. The host system may exchange I/O communications with physical storage devices and/or global memory over an I/O path that does not include any directors, for example, over the internal fabric to which the host system is directly attached. In embodiments in which at least a portion of the global memory is considered part of a director, the host system may be configured to communicate with such global memory over the internal fabric and without use of director compute resources.

Abstract: The invention relates to a method for providing data packets (5) from a CAN bus (2), in particular a charging station for a motor vehicle. In order to permit a resource-saving and nevertheless secure possible way of providing data packets (5), steps are provided: detection of the data packets (5) from at least one component (3) of the CAN bus (2) by a detection unit (10) which is part of the CAN bus (3), creation of at least one web resource (6) which contains the data packets (5) in accordance with a predetermined specification by a computing unit (11), wherein only data packets (5) which are related in accordance with the predetermined specification are combined in the at least one web resource (6), transmission of a content of the at least one web resource (6) from the computing unit (11) to a receiving device (4) by means of a communication unit (12) via a data link (7) having a transmission protocol that differs from the CAN bus (2).

Abstract: A system and method for providing system data during a power-on routine of a basic input output system. A controller is powered with an independent power source and accesses the system data. A power-on self-test routine is performed via a basic input output system. The fastest available interface of a plurality of interfaces between the basic input output system and the controller is determined. One of the plurality of interfaces is selected. The system data is sent from the controller to the basic input output system via the selected interface during the power-on self-test routine.

Abstract: The present disclosure generally relates to an interface transmitting training method and algorithm. The receiving device can train the transmitting device to choose the correct tap for transmitting from the transmitting device. During the training, the receiving device will send a request for a directional change tap. The transmitting device will note the request, but not act on the request. The receiving device will then send another request for a direction change tap. If the new request is for the same directional change tap as the previous request, and the number of consecutive identical directional change tap requests exceeds a predetermined threshold, the request is executed. By so doing, the effect of randomness for choosing the correct tap is minimized and the link is not degraded by transmitter training. As such, there is an overall improvement in the bit error rate and reliability of the serial interface.

Abstract: A system including an Ethernet transceiver PHY and a network device is disclosed. The Ethernet transceiver PHY includes register circuitry to store information associated with operating characteristics of the PHY. The network device couples to the Ethernet transceiver PHY in a closed system architecture and includes a system processor and an MDIO interface. The MDIO interface interacts with the PHY register circuitry during a normal operating mode. The system includes system interface circuitry to receive requests for accessing the register circuitry in a debug operating mode. The requests are generated external to the closed system architecture.