Abstract: Examples described herein generally relate to a Peripheral Connect Interconnect Express (PCIe) device. An example is a non-transitory memory storing a representation of a design that is to be implemented on a programmable integrated circuit. The design includes a classifier module (CM), a message trap engine module (MTEM), and a configuration space. The CM is capable of receiving a PCIe message and is configured to determine whether the PCIe message is a PCIe Type 1 configuration transaction. The CM is configured to forward the PCIe message to an endpoint device and to the MTEM when the PCIe message is a non-PCIe Type 1 configuration transaction and the PCIe Type 1 configuration transaction, respectively. The MTEM is configured to virtualize a downstream port(s) of a virtual switch and maintain the configuration space. The MTEM is capable of accessing the configuration space in response to the PCIe message.

Abstract: A rack switch coupling system includes a plurality of computing devices that are positioned in a rack in a stacked orientation. Each of the plurality of computing devices includes a top surface that corresponds with a first plane associated with that computing device, and a bottom surface that is located opposite that computing device from the top surface and that corresponds with a second plane associated with that computing device. The rack switch coupling system also includes a switch system that is positioned in the rack and that includes respective ports cabled to each of the plurality of computing devices, with each of the respective ports located adjacent the computing device to which it is cabled and between the first plane and the second plane associated with that computing device.

Abstract: An embedded controller is provided for a computer, including a processor, first one or more logic elements providing a serial peripheral interface (SPI) module to communicatively couple the embedded controller to an SPI bus as an SPI slave, and second one or more logic elements providing a platform environment control interface (PECI)-over-SPI engine, to build an SPI packet providing an encapsulated PECI command and send a notification to an SPI master that the packet is available.

Abstract: A memory subsystem is provided, including a memory controller integrated circuit (IC), a memory bus and a memory IC, all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport.

Abstract: An interface connection apparatus disposed in a first electronic device is provided that includes an analog physical layer circuit, a waveform generation circuit and a media access control circuit. The analog physical layer circuit receives an analog handshake signal from a second electronic device and generates a digital handshake signal. The waveform generation circuit determines whether a matching times that a pulse parameter of each of pulses included in the digital handshake signal is within a predetermined pulse parameter range reaches predetermine times and generates a digital output signal when the matching times reaches the predetermine times, and an output pulse parameter of all output pulses of the digital output signal is within the predetermined pulse parameter range. The media access control circuit determines that the analog handshake signal is valid when the media access control circuit receives the digital output signal to keep performing handshake.

Abstract: A device of the present invention, connected to a Communication Module (CM) via two signal lines, constructs a frame, formatted according to a second Communication Protocol (CP), from bit signals, which are being received from the CM via one signal line, corresponding to data of a frame of a particular format defined by a first CP, to transmit the constructed frame to a bus while transmitting data detected from the bus to the CM via the other signal line in the form of a frame of the particular format. The device measures a width of a pulse signal inserted at a predetermined position in a frame of the particular format being received from the CM first after power on, identifies a bit rate, based on the measured width, at which the CM transceiver data, and applies the identified bit rate to data communication with the CM.

Abstract: A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, from a driver of the host system, a request regarding a page of data stored in the second memory; responsive to the request, transfer the page from the second memory to a buffer; and write the page from the buffer to the first memory, wherein the page is written to the first memory during at least one of a second plurality of windows corresponding to a refresh timing for the memory bus, and the refresh timing is controlled at the host system.

Abstract: A peripheral device having a connector receptacle capable of identifying a master-slave mode includes a body and a connector module. The connector module includes a processing unit, an energy storage unit, and a connector receptacle. When the connector module is connected to an electronic device through a power positive terminal, a power negative terminal, a signal positive terminal, a signal negative terminal, and a transmission cable, the processing unit transmits a notification signal to the electronic device through the positive terminal of the signal and the negative terminal of the signal to notify the electronic device that the electronic device does not need to provide power to the peripheral device.

Abstract: Disclosed are an apparatus for data processing, an artificial intelligence chip, and an electronic device. The apparatus for data processing includes: at least one input memory, at least one data conveying component, at least one multiplexed arbitration component, and at least one output memory. The input memory is connected to the data conveying component, the data conveying component is connected to the multiplexed arbitration component, and the multiplexed arbitration component is connected to the output memory.

Abstract: A technique manages data storage equipment. The technique involves receiving queue depth metrics from data storage performance data describing data storage performance of the data storage equipment. The technique further involves performing a performance impact detection operation on the queue depth metrics to determine whether a performance impacting event has occurred on the data storage equipment. The technique further involves, in response to a result of the performance impact detection operation indicating that a performance impacting event has occurred on the data storage equipment, launching a set of performance impact operations to address the performance impacting event that occurred on the data storage equipment. Such a technique may be performed by an electronic apparatus coupled with the data storage equipment (e.g., over a network).

Abstract: According to some example embodiments, a system includes: at least one motherboard; at least one baseboard management controller (BMC); a mid-plane; and at least one storage device, wherein the at least one storage device is configured to operate in a first mode or a second mode based on a first input received from the at least one motherboard or the at least one BMC via a plurality of device ports over the mid-plane; and when operating in the second mode, the at least one storage device is configured to operate in a first speed from a plurality of operating speeds based on a second input received from the mid-plane via the plurality of device ports.

Abstract: The invention discloses a control circuit applied to a Universal Serial Bus (USB) which includes a first channel configuration pin and a second channel configuration pin. The control circuit includes: a first transistor having a first control terminal; a first resistor group coupled to the first channel configuration pin and the first transistor; a first Schottky diode having a first end and a second end, the first end being coupled to the first control terminal; a second transistor having a second control terminal; a second resistor group coupled to the second channel configuration pin and the second transistor; and a second Schottky diode having a third end and a fourth end, the third end being coupled to the second control terminal, and the fourth end being coupled to the second end of the first Schottky diode.

Abstract: An arrangement for providing a combined data and control signal for a multi die flash, comprising, a memory arrangement, the memory arrangement comprising at least two dies, a controller configured to send and receive signals to the memory arrangement and a common line connected to the memory arrangement and the controller and configured to transmit the signals from the controller to the at least two dies, wherein the arrangement is configured to provide a combined data and combined control signals to the multi-die flash.

Abstract: Certain aspects of the present disclosure provide a circuit for testing processor cores. For example, certain aspects provide a circuit having a deserializer having at least one input coupled to at least one input node of the circuit and having a first plurality of outputs, a plurality of processor cores having inputs coupled to the first plurality of outputs of the deserializer, and a serializer having inputs coupled to a second plurality of outputs of the plurality of processor cores.

Abstract: Disclosed are systems, computer-readable mediums, and methods for managing input-output operations within a system including at least one client and a storage system. A processor receives information regarding allocated input-output operations (IOPS) associated with a client accessing a storage system storing client data. The information includes a number of allocated total IOPS, a number of allocated read IOPS, and a number of allocated write IOPS. The processor also receives a requested number of write IOPS associated with the at least one client's request to write to the storage system. The processor determines a target write IOPS based on the number of allocated total IOPS, the number of allocated write IOPS and the requested number of write IOPS, and executes the determined target write IOPS within the first time period.

Abstract: A method and apparatus for performing memory access operations during a memory relocation in a computing system are disclosed. In response to initiating a relocation operation from a source region of memory to a destination region of memory, copying one or more lines of the source region to the destination region, and activating a mirror operation mode in a communication circuit coupled to one or more devices included in the computing system. In response to receiving an access request from a device, reading previously stored data from the source region, and in response to determining the access request includes a write request, storing new data included in the write request to locations in both the source and destination regions.

Abstract: Memory queues described herein use a single hardware and/or software architecture for a memory array. This memory array can be partitioned to be between one memory sub-array to implement a single memory queue and multiple memory sub-arrays to implement multiple memory queues. Various electrical signals provided by or provided to these multiple memory queues include addressing information to associate these various control signals with one or more of the multiple memory sub-arrays. In some situations, the memory queues can externally associate their corresponding read pointers to entries of one of their memory sub-arrays. In these situations, these memory queues can dynamically associate their read pointers to point to any entry from among their memory arrays and to read the data store therein starting from any random entry within their memory arrays.

Abstract: An information processing device includes: a first processing unit that processes plural color signals at a time and outputs a processed plural color signals in parallel; a memory that temporarily stores the processed plural color signals outputted in parallel from the first processing unit; and a second processing unit that reads the processed plural color signals from the memory in order by a processable number at a time, the second processing unit being able to process a smaller number of color signals than the first processing unit at a time, wherein a reading speed from the memory is faster than a writing speed to the memory.

Abstract: A method is performed to compile input data including a plurality of pulse sequences, hardware parameters obtained from a computing device, and a mathematical model with time-dependent control parameters to decrease a computation time of the input data. The method also includes providing the input data to the computing device to allow the computing device to run a computation of the input data. The method further includes converting the pulse sequences into memory-aligned arrays to decrease the computation time of the input data. The method includes calculating optimized output data using an adaptive step size computation to decrease the computation time needed to compute the output data.

Abstract: Programmable devices and methods of operation are disclosed. In some embodiments, a programmable device may include programmable logic selectively coupled to a plurality of input/output (I/O) interface circuits by a programmable interconnect fabric and a network-on-chip (NoC) interconnect system. The programmable logic may include configurable logic elements, programmable interconnects, and dedicated circuitry. The programmable interconnects may form part of the programmable interconnect fabric. In some embodiments, the programmable interconnect fabric selectively routes non-packetized data between the programmable logic and a first group of I/O interface circuits, and the NoC interconnect system selectively routes packetized data between the programmable logic and a second group of I/O interface circuits. The NoC interconnect system may operate according to a data packet protocol, and the second group of I/O interface circuits may include memory controllers compatible with the data packet protocol.