Abstract: Shared memory device apparatus and related methods are disclosed. An example method includes obtaining memory operation commands. The memory operation commands are received by a command dispatcher in a same order as obtained by the queue arbiter from the host device. The example method further includes separately and respectively queuing the memory operation commands for each of a plurality of memory devices and dispatching the memory operation commands for execution. The example method also includes receiving the dispatched memory operation commands at a plurality of command queues, where each command queue is associated with a respective one of the plurality of memory devices. Each command queue is configured to receive its respective dispatched memory operation commands from the command dispatcher in a same order as received by the dispatcher and provide the received memory operation commands to its respective memory device in a first-in-first-out order.

Abstract: A storage system maintains a journal of journal entries and at lease one snapshot of one or more data volumes. By assigning a unique sequence number to journal and snapshot, it is easy to find a journal which can be applied to the snapshot. A technique is described for detecting an overflow condition of running out of journal space and recovering the journal space.

Abstract: Some embodiments provide for a method of mapping a user design to a configurable integrated circuit (IC). The method is for a configurable IC that implements a user design with an associated user design clock cycle. The IC operates on a sub-cycle clock that has multiple sub-cycle periods within a user period of the user design clock cycle. The method identifies multiple port accesses to a first multi-port memory defined in the user design. The accesses are in a single user design clock cycle. The method maps the multiple port accesses to the first multi-port memory to multiple physical-port memory accesses to a second physical-port memory in the configurable IC during multiple sub-cycles associated with a single user design clock cycle.

Abstract: Improved thrashing aware and self configuring cache architectures that reduce cache thrashing without increasing cache size or degrading cache hit access time, for a DSP. In one example embodiment, this is accomplished by selectively caching only the instructions having a higher probability of recurrence to considerably reduce cache thrashing.

Abstract: Systems and methods, including computer software stored on a machine-readable medium for performing operations, can be implemented for allocating memory. Multiple channels are defined on a mobile device. Each channel can be adapted to receive a predetermined type of content for access on the mobile device. An amount of memory allocated to each channel for storing data is defined. Data identifying a new amount of memory allocated to one of the channels is received, and the amount of memory allocated to the channel is adjusted based on the data identifying the new amount of memory.

Abstract: Host page management assist functions are employed to manage storage of a pageable mode virtual environment. These functions enable storage to be managed by a processor of the environment absent intervention of a host of the environment. The functions include a resolve host page function; a pin function; and unpin functions.

Abstract: A management method, a management apparatus, and a controller for memory data access are provided. The management apparatus is disposed between a host and a device for managing the data transmitted between the host and the device, wherein the management apparatus includes a control unit and a storage unit. When the control unit receives a data writing command from the host, it searches for a set mapped to the data in the storage unit and updates the data in the set. Then, the control unit collects the other parts of the data in the storage unit and the device, integrates all parts of the data, and writes the integrated data into the device. Accordingly, the efficiency in data transmission can be improved, and the number of data writing operations can be reduced so that the lifespan of the device can be prolonged.

Abstract: The present disclosure includes, among other things, methods, systems, program products, and devices for providing access to memory in a system with memory protection. A request is received from a processor for a memory access at a first memory location. A second memory location is determined. The second memory location is associated with the first memory location and is protected from access by the processor. The requested memory access is performed at the second memory location.

Abstract: Methods, systems, and apparatus for storing and accessing data stored in a data array are presented. In one embodiment, data is stored in a data array that includes a plurality of nodes. The nodes of the data array are segmented into one or more standard and priority pages. The pages are represented in a packed index. The priority pages are then cached and the standard pages are saved to disk. In another embodiment, data stored in a node of a data array may be accessed wherein the data array is segmented into at least one priority page and at least one standard page and the data array includes a plurality of nodes. A request for data stored in the node may be received. A priority page and/or a standard page may be searched for the node and, when found, the node may be accessed.

Abstract: A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of the address banks share physical memory locations for at least one redundant most significant bit. Additionally, at least two of the address banks in certain embodiments share physical memory locations for at least one redundant most significant bit and at least one redundant least significant bit. At least two of the address banks in certain embodiments also share physical memory locations for at least one redundant interior bit.

Abstract: A method and apparatus for resolving volumes identifiers and drive letters associated with a virtual machine is described. In one embodiment, the method comprises correlating system registry information with at least one virtual drive configuration associated with a virtual machine image to produce a correlation result and mapping a volume identifier to at least one virtual drive based on the correlation result.

Abstract: A source-synchronous capture unit includes a data register unit to register data synchronized to a strobe or non-free running clock. The source synchronous capture unit also includes an asynchronous first-in-first-out (FIFO) unit to store the data from the data register unit in response to the strobe or non-free running clock and to output the data stored, in response to another clock.

Abstract: According to one embodiment, a semiconductor storage device includes a queuing buffer, a read module, a separating module, a write command issuing module, and a write module. The write command issuing module is configured to add a write address indicated by write pointer information to the management data obtained by the separating module in order to issue a write command, and to automatically queue the write command into the queuing buffer. The write module is configured to supply the write command issued by the write command issuing module to the nonvolatile memory in order to write data into the nonvolatile memory.

Abstract: A method controlling a memory card including a nonvolatile semiconductor memory including plural write areas. The method: formats the plural write areas; creates a temporary file entry describing a reserved region size including a free part of the plural write areas and a start position of the reserved region; writes a file in the reserved region from the start position after creating the temporary file entry; when the file has been completely written, determines size of the file written and writes a final file entry describing the start position and file size; when the file has not been completely written, references the temporary file entry to recognize the start position; detects a final position in the reserved region; determines size of the unfinished file using the start position and final position; changes the temporary file entry to a final entry describing the start position and unfinished file size.

Abstract: A tape recording apparatus is configured for sequentially recording files when receiving a command to write the files from an external host. The tape recording apparatus includes a buffer for temporarily storing the files, a tape on which the files are recorded, a writing device for writing the files stored in the buffer on the tape, and a writing control device for performing control of sequentially writing the files stored in the buffer on the tape one by one. The writing control device memorizes designated delimiter positions when delimiter position designation commands are received from the external host, the delimiter position designation commands designating the delimiter positions of the files to be sequentially written.

Abstract: Provided are a method, computer program product and system for determining an end of valid log in a log of write records. Records are written to a log in a storage device in a sequential order, wherein the records include a next pointer addressing a next record in a write order and a far ahead pointer addressing a far ahead record in the write order following the record. The far ahead pointer and the next pointer in a plurality of records are used to determine an end of valid log from which to start writing further records.

Abstract: A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.

Abstract: According to one embodiment, a memory controller comprises a counter and a setting module. The counter is configured to count the number of valid pages in a block includes a page to be invalidated, when data is written in a nonvolatile memory. The setting module is configured to set the block as an object of compaction when the number of valid pages counted by the counter is smaller than a predetermined number.

Abstract: Systems and processes may include a memory coupled to a memory controller. Command signals for performing memory access operations may be received. Attributes of the command signals, such as type, time lapsed since receipt, and relatedness to other command signals, may be determined. Command signals may be sequenced in a sequence of execution based on the attributes. Command signals may be executed in the sequence of execution.

Abstract: During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages.