Abstract: Systems and processes may be used to retrieve metadata from a nonvolatile memory of a portable device and transmit the retrieved metadata to an external host. Metadata may be analyzed using the external host and/or at least a portion of the metadata may be modified based on the analysis. Modified metadata may be transmitted from the external host to a memory controller of the host.

Abstract: A computer system includes multiple processing threads that execute in parallel. The multiple processing threads have access to a global environment including different types of metadata enabling the processing threads to carry out simultaneous execution depending on a currently selected type of lock mode. A mode controller monitoring the processing threads initiates switching from one type of lock mode to another depending on current operating conditions such as an amount of contention amongst the multiple processing threads to modify the shared data. The mode controller can switch from one lock mode another regardless of whether any of the multiple processes are in the midst of executing a respective transaction. A most efficient lock mode can be selected to carry out the parallel transactions. In certain cases, switching of lock modes causes one or more of the processing threads to abort and retry a respective transaction according to the new mode.

Abstract: A method for controlling a memory card which includes a nonvolatile semiconductor memory whose memory area includes a plurality of write areas is disclosed. A first area which is a part of the plurality of write areas is set in accordance with management executed by a first file system. The first file system sequentially writes data along a direction in which addresses of the plurality of write areas increase. A second area which is a part of the plurality of write areas is set in accordance with management executed by a second file system. The second file system writes data in an order which does not depend on the addresses.

Abstract: Systems and processes may include a first memory and a second memory. A driver and/or an application may be stored in the first memory. Flash memory type data of the first memory may be stored in the second memory. The driver may control the first memory at least partially based on the flash memory type data. The first memory may be exchanged for a third memory. The driver may be stored on the third memory. The flash memory type data for the third memory may be stored on the second memory.

Abstract: On-line storage devices are migrated to new storage devices in a non-disruptive manner. A host executing multipath I/O software is initially coupled to a source storage device via at least one active path. The target storage device is configured with the source device's device identification information. The target storage device is coupled to the host via a passive path so that the target storage device can return its device identification information to the host but cannot respond to I/O read or I/O write requests from the host. All paths between the host and the source storage device are then disconnected. An on-line data migration session between the source storage device and the target storage device is then activated. The path between the target storage device and the host is then re-configured from passive to active so that the target storage device can respond to I/O read and I/O write requests.

Abstract: When misses occur in an instruction cache, prefetching techniques are used that minimize miss rates, memory access bandwidth, and power use. One of the prefetching techniques operates when a miss occurs. A notification that a fetch address missed in an instruction cache is received. The fetch address that caused the miss is analyzed to determine an attribute of the fetch address and based on the attribute a line of instructions is prefetched. The attribute may indicate that the fetch address is a target address of a non-sequential operation. Another attribute may indicate that the fetch address is a target address of a non-sequential operation and the target address is more than X % into a cache line. A further attribute may indicate that the fetch address is an even address in the instruction cache. Such attributes may be combined to determine whether to prefetch.

Abstract: Performing a backup of a stub object located on a file system managed by a hierarchical storage manager configured to migrate data objects from the file system to a migration storage pool. The stub object includes information for recalling a migrated data object and is configured to determine whether a backup copy of the migrated data object is stored in a backup storage pool if the backup is performed in an incremental backup operation. The backup further includes directing the hierarchical storage manager to recall the migrated data object to the file system if the backup copy of the migrated data object is not stored in the backup storage pool or if the backup is performed in a selective backup operation. The backup additionally includes storing a backup copy of the migrated data object in the backup storage pool if the migrated data object is recalled.

Abstract: A method and system for saving and retrieving data includes saving data in data storage fields of a data storage device in a computer. A back-up data storage field is selected in the data storage device. A data changing operation including new data is initiated on specified data saved in a current data storage field. A copy of all the data stored in boundary data storage fields is copied and stored in the back-up data storage field before changing the current data to provide data retrieval if the data is unrecoverable in the current data storage field, when a loss of power to the data storage device occurs.

Abstract: A data writing method for a flash memory is provided. The data writing method includes following steps. First, a block is selected as a substitute block from a spare area of the flash memory, wherein the substitute block is used for substituting a data block in a data area for writing a new data. Next, the new data is directly written into the substitute block starting from a start page, wherein there is valid data in the data block before the address for writing the new data. Thereby, meaningless data moving can be reduced, system performance can be improved, and overlong waiting time for writing the new data can be prevented.

Abstract: Embodiments include methods, apparatus, and systems for managing snapshots in storage systems. One method includes logically linking a plurality of snapshots to a logical disk in a storage network; and splitting the snapshots from the logical disk to form a snapshot tree that includes the snapshots split from the logical disk.

Abstract: Method and system for a multi-level virtual/real cache system with synonym resolution. An exemplary embodiment includes a multi-level cache hierarchy, including a set of L1 caches associated with one or more processor cores and a set of L2 caches, wherein the set of L1 caches are a subset of the set of L2 caches, wherein the set of L1 caches underneath a given L2 cache are associated with one or more of the processor cores.

Abstract: Embodiments of the present invention provide a system that executes transactions on a processor that supports transactional memory. The system starts by executing the transaction on the processor. During execution of the transactions, the system places stores in a store buffer. In addition, the system sets a stores_encountered indicator when a first store is placed in the store buffer during the transaction. Upon completing the transaction, the system determines if the stores_encountered indicator is set. If so, the system signals a cache to commit the stores placed in the store buffer during the transaction to the cache and then resumes execution of program code following the transaction when the stores have been committed. Otherwise, the system resumes execution of program code following the transaction without signaling the cache.

Abstract: For NAND flash devices, two specific bounds for the program time are defined in the data sheets: a typical program time, during which more than 50% of all pages are programmed, and a maximum program time. Reduction of the maximum program time to an effective program time is possible using the following method for writing to a flash memory, comprising the steps of specifying an effective program time that is between typical and maximum program time, writing first data to the flash memory, after the effective program time checking if the programming cycle is finished, if it is finished writing second data to the flash memory, and if it is not finished writing the at least second data to a buffer memory and marking them as not to be overwritten, repeating the previous steps as long as further data are to be stored, determining a free location in a flash memory, and copying the at least second data from the buffer memory to the determined location in the flash memory.

Abstract: A method, apparatus and system of a hierarchy of a structure of a volume is disclosed. In one embodiment, a system includes a physical volume, a structure to provide a mapping to a location of a data segment of the physical volume that may include a table having a hierarchy, a logical volume management module to define a logical volume as an arrangement of the physical volume, a snapshot module that may automatically generate a point-in-time image of the logical volume, may prompt the logical volume management module to create and insert a first table and a second table into the hierarchy of the structure, the first table may provide a set of updates to the logical volume, the second table may provide a set of updates to the point-in-time image, and a data processing system to perform a write IO (Input/Output) operation and a read IO operation.

Abstract: Versatility of a memory card is improved by providing a memory card where data protection mode and normal mode can be selected at discretion. A portable auxiliary storage device includes a mode setting section, a mode detecting section and a memory access control section. The mode setting section allows a user to set a normal mode permitting reading data stored in a memory section or writing the data to the memory section without restriction and a data protection mode for restricting the reading or writing. The mode detecting section detects a mode set in the mode setting section. The memory access control section controls the read or write according to a state of the mode setting section detected by the mode detecting section.

Abstract: High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.

Abstract: A high-capacity memory subsystem architecture utilizes multiple memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.

Abstract: A processor-based system includes a processor coupled to a system controller through a processor bus. The system controller is used to couple at least one input device, at least one output device, and at least one data storage device to the processor. Also coupled to the processor bus is a memory hub controller coupled to a memory hub of at least one memory module having a plurality of memory devices coupled to the memory hub. The memory hub is coupled to the memory hub controller through a downstream bus and an upstream bus. The downstream bus has a width of M bits, and the upstream bus has a width of N bits. Although the sum of M and N is fixed, the individual values of M and N can be adjusted during the operation of the processor-based system to adjust the bandwidths of the downstream bus and the upstream bus.

Abstract: A source-synchronous capture unit includes a data register unit to register data synchronized to a strobe or non-free running clock. The source synchronous capture unit also includes an asynchronous first-in-first-out (FIFO) unit to store the data from the data register unit in response to the strobe or non-free running clock and to output the data stored, in response to another clock.

Abstract: A method for merging data including receiving a request from an input/output device to merge a data, wherein a merge of the data includes a manipulation of the data, determining if the data exists in a local cache memory that is in local communication with the input/output device, fetching the data to the local cache memory from a remote cache memory or a main memory if the data does not exist in the local cache memory, merging the data according to the request to obtain a merged data, and storing the merged data in the local cache, wherein the merging of the data is performed without using a memory controller within a control flow or a data flow of the merging of the data. A corresponding system and computer program product.