Abstract: Certain aspects of a method and system for combining page buffer list entries (PBLEs) to optimize caching of translated addresses are disclosed. Aspects of a method may include encoding at least two page buffer list entries in a remote direct memory access (RDMA) memory map into at least two contiguous memory locations by utilizing a remainder of a physical address corresponding to the two page buffer list entries. The first memory location of the two contiguous memory locations may comprise a base address and a contiguous length of the first page buffer list entry. The second memory location of the two contiguous memory locations may comprise a virtual address and a contiguous length of the second page buffer list entry.

Abstract: Data is written in data areas (202) and information for correcting an error of the data and status information indicating that the data has been written are written in redundant areas (203) sequentially from the first page of a physical block (201). In the step of creating information to be written in the physical block (201), the redundant areas (203) of the pages are subjected to a binary search to temporarily identify a last valid page. Further, the contents of every area (the data areas and the redundant areas) of the temporarily identified last valid page and a page adjacent to the temporarily identified last valid page are checked to finally identify the last valid page and make a judgment as to whether or not an error page resulting from power-down exists.

Abstract: Systems and processes may include a memory coupled to a memory controller. Command signals for performing memory access operations may be received. Attributes of the command signals, such as type, time lapsed since receipt, and relatedness to other command signals, may be determined. Command signals may be sequenced in a sequence of execution based on the attributes. Command signals may be executed in the sequence of execution.

Abstract: In the case in which data in a storage system A is remotely copied to a storage system B, it is not taken into account whether the data of the remote copy is WORM data. In the case in which a setting is made such that data stored in a volume in the storage system A is copied to a volume in the storage system B, storage system A judges whether an attribute to the effect that data can be referred to and can be updated or to the effect that data can be referred to but cannot be updated is added to the volume in the storage system A. Then, if the volume is a volume to which the attribute to the effect that data can be referred to but cannot be updated is added, such attribute is added to the volume in the storage system B.

Abstract: A control program download device is disclosed that is to be connected to a host computer and to one or more external devices having predetermined functions so as to download a control program for controlling the external device from the host computer to a rewritable internal memory circuit. The control program download device comprises an external setting unit in which external information indicating the connection to the external device is preset, an external memory unit into which the external information is loaded from the external setting unit in response to a control signal input to the external memory unit, and a download control unit that controls download of the control program to the internal memory circuit.

Abstract: A storage device includes: a binary flash memory that has a first storage area and a capacity of storing two values per cell; a multivalued flash memory that has a second storage area and a capacity of storing at least three values per cell; and a controller configured to arrange the first storage area ahead of the second storage area, logically combine the first storage area with the second storage area to form a single combined storage area, and perform data reading and data writing from and into the combined storage area. Data management information is stored in a head of the combined storage area according to a predetermined file system. The storage device of this arrangement has the advantages of both an SLC flash memory and an MLC flash memory.

Abstract: Systems and methods of addressing two or more banks of memory utilizing a single-bank serial peripheral interface and an at least three-byte address protocol are provided. In one embodiment, a serial peripheral interface comprises a serial processing component configured to address one of the memory banks using the three-byte addressing scheme, and to write data to or read data from the addressed bank, and a bank register pointer component coupled to the serial processing component, the pointer component comprising two or more bank register pointers associated with respective memory banks, and configured to select one of the memory banks based on the two or more bank register pointers, wherein the bank register pointer component selects one of the two or more memory banks, and the serial processing component writes data to or reads data from the selected bank of memory according to the three-byte addressing scheme.

Abstract: Software indicates to hardware of a processing system that its storage modification to a particular cache line is done, and will not be doing any modification for the time being. With this indication, the processor actively releases its exclusive ownership by updating its line ownership from exclusive to read-only (or shared) in its own cache directory and in the storage controller (SC). By actively giving up the exclusive rights, another processor can immediately be given exclusive ownership to that said cache line without waiting on any processor's explicit cross invalidate acknowledgement. This invention also describes the hardware design needed to provide this support.

Abstract: Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.

Abstract: Resolving retention policy conflicts is disclosed. An indication is received that two or more retention policies apply to an item of content. A merged retention policy that is based at least in part on the respective requirements of the two or more retention policies is generated automatically for the item of content.

Abstract: Methods and apparatus allowing a choice of Least Frequently Used (LFU) or Most Frequently Used (MFU) cache line replacement are disclosed. The methods and apparatus determine new state information for at least two given cache lines of a number of cache lines in a cache, the new state information based at least in part on prior state information for the at least two given cache lines. Additionally, when an access miss occurs in one of the at least two given lines, the methods and apparatus (1) select either LFU or MFU replacement criteria, and (2) replace one of the at least two given cache lines based on the new state information and the selected replacement criteria. Additionally, a cache for replacing MFU cache lines is disclosed.

Abstract: A method for performing backup of a stub object located on a file system managed by a hierarchical storage manager configured to migrate data objects from the file system 10 a migration storage pool includes determining whether a backup copy of the migrated data object is stored in a backup storage pool if the backup is performed in an incremental backup operation. The storage manager recalls the migrated data object to the file system if the backup copy of the migrated data object is not stored in the backup storage pool or if the backup is performed in a selective backup operation. If the migrated data object is recalled, the backup copy of the migrated data object is created and stored in the backup storage pool. If the migrated data object is not recalled, a backup copy of the stub object is created and stored in the backup storage pool.

Abstract: A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance.

Abstract: A computer readable medium is provided embodying instructions executable by a processor to perform a method for performing a transaction including a transaction head and a transaction tail, the method includes executing the transaction head, including executing at least one memory reserve instruction to reserve a transactional memory location that are accessed in the transaction and executing the transaction tail, wherein the transaction cannot be aborted due to a data race on that transactional memory location while executing the transaction tail, wherein data of memory write operations to the transactional memory location is committed without being buffered.

Abstract: An apparatus and method for managing a mapping table of a non-volatile memory are provided. The apparatus includes a non-volatile memory having memory cells, each of which stores data bits in a plurality of pages included in a block according to a plurality of states, each of which has at least two bits, an operating time measuring unit measuring a write operation time on each of the plurality of pages included in the block, and a mapping table generating unit dividing the pages into a plurality of groups according to the measured write operation time and generating a mapping table by using the divided groups.

Abstract: A storage subsystem, method of automatically maintaining the subsystem hardware configuration up to date and program product therefor. The storage subsystem automatically initiates hardware discovery in response to a triggering event. Subsystem hardware information is collected during hardware discovery and checked against a current configuration to identify hardware changes. Whenever hardware changes are identified, the subsystem configures the hardware and calibrates newly configured hardware. So, hardware changes may be automatically discovered, configured and calibrated free from operator intervention.

Abstract: Systems and methods that manage memory are provided. In one embodiment, a system for communications may include, for example, a memory management system that may handle a first application employing a virtual address based tagged offset and a second application employing a zero based tagged offset with a common set of memory algorithms.

Abstract: In a storage system adopting an external storage connection configuration, a first storage apparatus is capable of integrally managing the cache residency settings made in second storage apparatuses, which serve as external storage apparatuses. The first storage apparatus stores the cache residency information for the second storage apparatuses, i.e., external storage apparatuses, in a shared memory thereof. When the storage system receives a cache residency setting request from a management device or the like, the first storage apparatus issues a cache residency setting instruction to a second storage apparatus with reference to the residency information. In accordance with the setting instruction, the second storage apparatus sets a cache-resident area in a cache memory thereof.

Abstract: A system and method for pre-fetching data from system memory. A multi-core processor accesses a cache hit predictor concurrently with sending a memory request to a cache subsystem. The predictor has two tables. The first table is indexed by a portion of a memory address and provides a hit prediction based on a first counter value. The second table is indexed by a core number and provides a hit prediction based on a second counter value. If neither table predicts a hit, a pre-fetch request is sent to memory. In response to detecting said hit prediction is incorrect, the pre-fetch is cancelled.

Abstract: A computing system that includes a number of processing elements, a memory and a multi-task controller. The memory is organized into a set of logical partitions. Task partitions describe a task and include task state information, task data registers and ASCII task instructions. The task state information includes a set of index registers that are accessible by the task instructions. The index registers typically have dedicated locations in the task partition and are referred to by lower case ASCII alphabetic characters. Index registers are used to refer to a task partition in some cases or to a location in the current task partition in other cases for purposes of branching. Index registers can be incremented or decremented and loaded with an immediate data value. In one embodiment, the data flow unit is used to interpret the branch code and fetch contents of a named index register used in the branch.