Abstract: The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.

Abstract: A system and method for using a local virtual disk for a virtual machine may include establishing a local virtual disk on a storage device of a host machine. The system and method include creating an access table and a location table. The access table includes access values indicative of data being accessed. The location table includes location values indicative of a location of the data in the local virtual disk or a shared storage space. A transfer of data between the local virtual disk and the shared storage space is done using the access table and the location table. The data is accessible in both the local virtual disk and the shared storage space based on the one or more location values of the location table and access to the data is based on the one or more access values of the access table.

Abstract: A system and method include receiving a request to transfer data from a first storage space to a second storage space. The system and method also include creating an access table and a location table. The access table includes one or more access values indicative of data being accessed. The location table includes one or more location values indicative of a location of the data in the first storage space or the second storage space. The system and method also include transferring data between the first storage space and the second storage space using the access table and the location table. The data is accessible on both the first storage device the second storage device based on the one or more location values of the location table and access to the data is based on the one or more access values of the access table.

Abstract: A coordination point for assigning clients to remote backup storages includes a persistent storage and a processor. The persistent storage stores gateway pool cache capacities of the remote backup storages. The processor obtains a data storage request for data from a client of the clients; obtains an indirect cache estimate for servicing the data storage request; selects a remote backup storage of the remote backup storages based on the obtained indirect cache estimate using the gateway pool cache capacities; and assign the selected remote backup storage to service the data storage request. The selected remote backup storage has a higher client load at a time selection than a second client load of a second remote backup storage of the remote backup storages.

Abstract: A first rank includes a plurality of first semiconductor memory devices, and a second rank includes a plurality of second semiconductor memory devices. The command/address signal lines are shared by a controller, the first rank, and the second rank, and the data lines are shared by the controller, the first rank, and the second rank. When performing a data movement operation of moving data between the first rank and the second rank, the controller applies a shift read command to one of the first rank and the second rank through the command/address signal lines and applies a normal write command or a shift write command to another of the first rank and the second rank through the command/address signal lines after a time corresponding to a value obtained by subtracting the value of the write latency from the value of the read latency.

Abstract: Dynamic resource partitioning techniques may include receiving a plurality of performance goals for a plurality of consumers, each of the plurality of performance goals denoting a performance goal for a different one of the plurality of consumers; performing first processing to determine whether one or more of a plurality of subsystems are overloaded and whether there is at least a first consumer of the plurality of consumers violates a corresponding one of the plurality of performance goals specified for said first consumer; and responsive to determining that one or more of the plurality of subsystems are overloaded and that at least a first consumer is not meeting the corresponding one of the plurality of performance goals specified for said first consumer, performing second processing to reduce workload directed to each of the one or more subsystems that are overloaded.

Abstract: Provided herein may be a storage device and a method of operating the same. A memory controller for controlling a memory device including a plurality of memory blocks having improved read performance may include a random read workload control, unit configured to control a state of a random read workload such that the random read workload is in any one of a set state and a clear state depending on a random read count obtained by counting a number of random read requests that are inputted from an external host; and a random read processing unit configured to retrieve a physical address corresponding to a logical address of the respective random read requests depending on the state of the random read workload.

Abstract: Systems and procedures are provided to enable large size fixed block architecture (FBA) device support over FICON. The FBA devices may have a size greater than 2 terabytes. For example, in known storage systems, an FBA device size may be 64 terabytes and an architecture provided for 512-terabyte devices, and the described system supports such large, or even larger, FBA devices. The system may be used with existing fixed block command sets.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0's in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.

Abstract: A system and method are disclosed with the ability to track usage of information, which patterns, and determine the most frequently used patterns to be stored and updated in a directory, thereby controlling and reducing the size allocated to storing information in the directory. The size is reduced by limiting address bits thereby allowing subsystems to avoid transmitting, storing, and operating upon excessive address information.

Abstract: A system and method are disclosed with the ability to track usage of information and determine commonly used patterns to be stored and updated in a directory. The information includes counter values that represent the frequency of occurrence of a pattern that is committed to the directory. Thus, allows the system to control and reduce the size allocated to storing information in the directory because the size is reduced by limiting address bits. This, in turn, creates additional benefits in speed and power because it allows subsystems to avoid transmitting, storing, and operating upon excessive address information.

Abstract: An apparatus is described. The apparatus includes a main memory controller having a point-to-point link interface to couple to a point-to-point link. The point-to-point link is to transport system memory traffic between said main memory controller and a main memory. The main memory controller includes at least one of compression logic circuitry to compress write information prior to being transmitted over the link; decompression logic circuitry to decompress read information after being received from the link.

Abstract: A memory subsystem empirically tests performance parameters of I/O with a memory device. Based on the empirical testing, the memory subsystem can set the performance parameters specific to the system in which the memory subsystem is included. A test system performs the testing. For each of multiple different settings for multiple different I/O circuit parameters, the test system sets a value for each I/O circuit parameter, generates test traffic to stress test the memory device with the parameter value(s), and measures an operating margin for the I/O performance characteristic. The test system further executes a search function to determine values for each I/O circuit parameter at which the operating margin meets a minimum threshold and performance of at least one of the I/O circuit parameters is increased. The memory subsystem sets runtime values for the I/O circuit parameters based on the search function.

Abstract: A memory controller includes a current information storage unit storing information about various current amounts of a memory system, a current management unit controlling an output time of an operation execution signal by calculating the information about the various current amounts, and a command controller outputting a command to operate a memory device in response to the operation execution signal.

Abstract: The embodiments of the present disclosure identify a target chip from among multiple chips coupled to a shared bus and customize an optimization parameter for the particular chip. Stated differently, in a communication system where only one chip (or a subset of chips) on a shared bus is the intended target, the system can customize an optimization parameter for the specific location of the target chip on the bus. As new data is received that is intended for a different chip—i.e., the target chip changes—the system can dynamically change the parameter based on the location of the new target chip on the bus.

Abstract: A method for recovering storage object records in solid state memory. The method includes, for each memory location of a solid state memory region, reading data fragment metadata and identifying, based on the data fragment metadata, a storage object. The storage object occupies a subset of memory locations of the memory locations of the solid state memory region. The method further includes identifying a first and a last memory location of the subset of memory locations, and restoring a storage object record for the storage object, wherein the storage object record comprises variables that enable a logical to physical address translation for the storage object.

Abstract: A method for preventing data loss in target volumes of copy service functions is disclosed. In one embodiment, such a method includes detecting a copy service function that copies data from a source volume to a target volume. The method automatically creates, in a different address space than the source volume and target volume, a shadow volume to receive data overwritten on the target volume. The method further automatically establishes a point-in-time copy relationship between the target volume and the shadow volume to preserve data on the target volume as writes are received thereto. A corresponding system and computer program product are also disclosed.

Abstract: A distributed storage system including memory hosts and at least one curator in communication with the memory hosts. Each memory host has memory, and the curator manages striping of data across the memory hosts. In response to a memory access request by a client in communication with the memory hosts and the curator, the curator provides the client a file descriptor mapping data stripes and data stripe replications of a file on the memory hosts for remote direct memory access of the file on the memory hosts.

Abstract: A memory system of a data processing system includes one or more storage devices and a data rearrangement engine for moving data between memory regions of the plurality of memory regions. The data rearrangement engine is configured to rearrange data stored at non-contiguous addresses in a source memory region into contiguous address in a destination region responsive to a rearrangement specified by a host processing unit of the data processing system. A description of the rearranged data is maintained in a metadata memory region. Rearranged data may be accessed by one or more host processing units. Write-back of data from the destination to the source region may be reduced by use of Bloom filter or the like.

Abstract: A technique allocates storage from a plurality of storage pools of a data storage assembly to host storage. The technique involves receiving an allocation request and, in response to the allocation request, performing a set of probability-based allocation attempt operations that attempts to allocate a storage portion from one of the plurality of storage pools to the host storage. Each storage pool of the plurality of storage pools provides multiple storage portions of physical storage to store host data. The technique further involves, based on a result of the set of probability-based allocation attempt operations, provisioning the host storage with a storage portion from a particular pool of the plurality of storage pools to satisfy the allocation request.