Patents Examined by Hien N Nguyen
  • Patent number: 11224767
    Abstract: One embodiment is directed to a non-contact, medical ultrasound therapy system for generating and controlling low frequency ultrasound. The ultrasound therapy system includes a treatment wand including an ultrasonic transducer, a generator unit, and a cable coupling the treatment wand to the generator unit. The generator unit generates electric power output to drive the ultrasonic transducer and includes a digital frequency generator, wherein the generator unit digitally controls energy output at resonance frequency of the ultrasonic transducer.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: January 18, 2022
    Assignee: SANUWAVE HEALTH, INC.
    Inventors: Ross Loven, Jeff Sampson, Li Qin, Ryan Glen Tetzloff, Douglas Duchon
  • Patent number: 11227654
    Abstract: A semiconductor device includes memory devices respectively comprising a selector transistor in series with a control transistor and a memory cell, wherein the control transistor is connected to the memory cell. Control lines of the semiconductor device extend along a first direction, and a first control line is connected to a first memory device control transistor and a second memory device control transistor. Word lines extend in the first direction, and a first word line is connected to a first memory device selector transistor and a second memory device selector transistor. Bitlines extend in a second direction, with a first bitline connected to a first memory device memory cell and a second bitline is connected to a second memory device memory cell. Source lines extend in the second direction, and a first source line is connected to the first memory device selector transistor and the second memory device selector transistor.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: January 18, 2022
    Assignee: Crossbar, Inc.
    Inventor: Hagop Nazarian
  • Patent number: 11222690
    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple levels of two-transistor (2T) memory cells vertically arranged above a substrate. Each 2T memory cell includes a charge storage transistor having a gate, a write transistor having a gate, a vertically extending access line, and a single bit line pair. The source or drain region of the write transistor is directly coupled to a charge storage structure of the charge storage transistor. The vertically extending access line is coupled to gates of both the charge storage transistor and the write transistor of 2T memory cells in multiple respective levels of the multiple vertically arranged levels. The vertically extending access line and the single bit line pair are used for both write operations and read operations of each of the 2T memory cells to which they are coupled.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: January 11, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Haitao Liu, Karthik Sarpatwari, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11217305
    Abstract: A nonvolatile memory device includes; a memory cell array including memory cells connected with bit lines and feedback cells connected with feedback bit lines, a row decoder connected with the memory cells and the feedback cells through word lines, a column decoder connected with the memory cells through the bit lines and connected with the feedback cells through the feedback bit lines, and a charge pump that generates a pump voltage provided to a selected word line among the word lines, wherein the charge pump is controlled in response to feedback currents flowing through the feedback bit lines.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: January 4, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Artur Antonyan
  • Patent number: 11211127
    Abstract: An apparatus, disclosed herein, comprises a plurality of planes, each plane of the plurality of planes including a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: determine a position of a program loop in a sequence of program loops performed to complete a programming operation; initiate an inhibit bit line ramping event for the first plane including ramping of a set of bit lines of a first plane up to an inhibit voltage and based on the position of the program loop, initiate an inhibit bit line ramping event with a ramping start time delay for a second plane, where the inhibit bit line ramping event for the second plane includes initiating ramping of a set of bit lines of the second plane up to the inhibit voltage after the ramping start time delay.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: December 28, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Yu-Chung Lien, Hua-Ling Hsu, Huai-Yuan Tseng
  • Patent number: 11205414
    Abstract: First data comprising a first range of audio frequencies is received. The first range of audio frequencies corresponds to a predetermined cochlear region of a listener. Second data comprising a second range of audio frequencies is also received. Third data comprising a first modulated range of audio frequencies is acquired. The third data is acquired by modulating the first range of audio frequencies according to a stimulation protocol that is configured to provide neural stimulation of a brain of the listener. The second data and the third data are arranged to generate an audio composition from the second data and the third data.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: December 21, 2021
    Assignee: BRAINFM, INC.
    Inventor: Adam Hewett
  • Patent number: 11200922
    Abstract: Various implementations described herein are related to a device having memory circuitry and multiplexer circuitry. The memory circuitry may include a single bank of memory cells that are arranged in multiple columns, and each column of the multiple columns may provide singe-bit data. The multiplexer circuitry may include multiplexer logic that receives the single-bit data from each column of the multiple columns and provides selected data as output data.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: December 14, 2021
    Assignee: Arm Limited
    Inventors: Sriram Thyagarajan, Andy Wangkun Chen, Yew Keong Chong, Munish Kumar
  • Patent number: 11194505
    Abstract: According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: December 7, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jun Gyu Lee, Reum Oh, Ki Heung Kim, Moon Hee Oh
  • Patent number: 11195582
    Abstract: A non-volatile memory device includes: a memory group of a plurality of variable resistance memory cells in which digital data is recorded according to a magnitude of a resistance value, the memory group including at least one data cell and at least one dummy cell which are associated with each other; and a read circuit which performs, in parallel, a read operation on each of the plurality of memory cells included in the memory group. Dummy data, for reducing a correlation between a side-channel leakage generated when the read operation is performed by the read circuit and information data recorded in the at least one data cell, is recorded in the at least one dummy cell.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: December 7, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Yuhei Yoshimoto, Yoshikazu Katoh, Naoto Kii
  • Patent number: 11185719
    Abstract: A system and method for controlling acoustic energy deposition in various media or objects are disclosed. The system and method can generate an acousto-mechanical or acousto-elastic effect in the various media or objects. The acousto-mechanical or acousto-elastic effect can induce a fragmentation of the media or objects.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: November 30, 2021
    Assignee: Guided Therapy Systems LLC
    Inventors: Michael H. Slayton, Paul Jaeger
  • Patent number: 11183239
    Abstract: An operation method of a resistive memory device includes receiving write data and an address; determining whether the write data is in a first state or in a second state; applying a first pulse to a target memory cell corresponding to the address, among a plurality of memory cells, when the write data is in the first state; and selectively applying, when the write data is in the second state, a second pulse to the target memory cell according to a comparison result of the write data and pre-read data which is pre-stored data read from the target memory cell.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: November 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Ho-Seok Em
  • Patent number: 11183252
    Abstract: A dynamic voltage supply circuit of a nonvolatile memory device includes a voltage amplification/output circuit and a dynamic voltage output circuit. The voltage amplification/output circuit receives a first clock signal and a second clock signal to generate a dynamic supply voltage greater than a supply voltage while the first clock signal has a “low” level. The dynamic voltage output circuit outputs the dynamic supply voltage while the first clock signal has a “low” level and outputs a ground voltage while the first clock signal has a “high” level.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: November 23, 2021
    Assignee: SK Hynix system ic Inc.
    Inventor: Hyun Min Song
  • Patent number: 11183240
    Abstract: A programmable resistive memory element and a method of adjusting a resistance of a programmable resistive memory element are provided. The programmable resistive memory element includes at least one resistive memory element. Each resistive memory element includes an Indium-Gallium-Zinc-Oxide (IGZO) resistive layer, a first electrical contact and a second electrical contact. The first and second electrical contacts are disposed on the IGZO resistive layer in the same plane. The programmable resistive memory element includes a voltage generator coupled to the first and second electrical contacts, constructed and arranged to apply a thermal treatment to the resistive memory element to adjust a resistance of the resistive memory element.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: November 23, 2021
    Assignee: CYBERSWARM, INC
    Inventors: Viorel-Georgel Dumitru, Cristina Besleaga Stan, Alin Velea, Aurelian-Catalin Galca
  • Patent number: 11179097
    Abstract: Tactile sensing devices, systems, and methods to image a target tissue location are disclosed. When force is applied to the tactile sensing device, voltage data is detected and visualized on a screen, indicating the target tissue location.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: November 23, 2021
    Assignee: TEXAS MEDICAL CENTER
    Inventors: Nicole C. Moskowitz, Jessica Traver, Xavier Garcia-Rojas, Yashar Ganjeh
  • Patent number: 11176994
    Abstract: Embodiments include apparatuses, methods, and systems to implement a multi-read and/or multi-write process with a set of memory cells. The set of memory cells may be multiplexed with a same sense amplifier. As part of a multi-read process, a memory controller coupled to a memory circuit may precharge the bit lines associated with the set of memory cells, provide a single assertion of a word line signal on the word line, and then sequentially read data from the set of memory cells (using the sense amplifier) based on the precharge and the single assertion of the word line signal. Additionally, or alternatively, a multi-write process may be performed to sequentially write data to the set of memory cells based on one precharge of the associated bit lines. Other embodiments may be described and claimed.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Muhammad M. Khellah, Somnath Paul, Charles Augustine, Turbo Majumder, Suyoung Bang
  • Patent number: 11173004
    Abstract: A multifunctional robotic system for performing in vivo procedures includes a control unit comprising a computer processor and a robotic arm in communication with the control unit for multi-axis movement of the robotic arm. The robotic arm has a plurality of passages therein. A printer head is disposed in one of the passages and is configured to create multi-dimensional objects in vivo. The robotic system includes a measuring system disposed in one of the passages. The computer processor has executable software configured to receive signals from the measuring system and is configured to control the printer head and the measuring system to position the object in an in vivo location based upon the signals from the measuring system.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: November 16, 2021
    Assignee: MIRAKI INNOVATION THINK TANK, LLC
    Inventors: Christopher J. Velis, Matthew P. Palmer, Adeel Saleem Shafi, Santosh Iyer
  • Patent number: 11176999
    Abstract: According to one embodiment, a semiconductor memory device includes first to nth string units (n being a natural number of 3 or more), a plurality of layers of word lines, and (n?1) layers of select gate layers. The first to nth string units each includes a memory string. The memory string includes a plurality of memory cells and a plurality of select transistors connected in series in a first direction. The (n?1) layers of select gate layers include first to (2×(n?1))th select gates electrically isolated from each other. The first string unit is selected by the first to (n?1)th select gates. The kth string unit (k being not less than 1 and not more than n) is selected by the kth to (n+k?2)th select gates. The nth string unit is selected by the nth to (2×(n?1))th select gates.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: November 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Noboru Shibata, Kazuaki Isobe
  • Patent number: 11172860
    Abstract: A computer implemented method for processing measurement data from electrocardiogram, ECG, electrodes on a subject. The method includes obtaining a 3D anatomical model of the torso of the subject, and obtaining a 3D image of the torso of the subject. The three dimensional image is aligned with the three-dimensional model. A position of each electrode in the three-dimensional model is determined from the three dimensional image. The positions of the electrodes in the three dimensional model are used for estimating the distribution, fluctuation and/or movement of electrical activity through heart tissue.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: November 16, 2021
    Assignee: PEACS INVESTMENTS B.V.
    Inventors: Peter Michael van Dam, Eelco Mattias van Dam
  • Patent number: 11170850
    Abstract: Methods, systems, and apparatus that support efficient utilization of die area for cross-point memory architecture are described. A memory array may include active memory cells overlying each portion of the substrate that includes certain types of support circuitry, such as decoders and sense amplifiers. Boundary tiles, which may be portions of an array having a different configuration from other portions of the array, may be positioned on one side of an array of memory tiles. The boundary tiles may include support components to access both memory cells of neighboring memory tiles and memory cells overlying the boundary tiles. Column lines and column line decoders may be integrated as part of a boundary tile. Access lines, such as row lines may be truncated or omitted at or near borders of the memory portion of the memory device.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Christophe Vincent Antoine Laurent
  • Patent number: 11165012
    Abstract: A magnetic memory including a first spin-orbital-transfer-spin-torque-transfer (SOT-SIT) hybrid magnetic device disposed over a substrate, a second SOT-STT hybrid magnetic device disposed over the substrate, and a SOT conductive layer connected to the first and second SOT-STT hybrid magnetic devices. Each of the first and second SOT-STT hybrid magnetic devices includes a first magnetic layer, as a magnetic free layer, a spacer layer disposed under the first magnetic layer, and a second magnetic layer, as a magnetic reference layer, disposed under the spacer layer. The SOT conductive layer is disposed over the first magnetic layer of each of the first and second SOT-STT hybrid magnetic devices.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: November 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ji-Feng Ying, Jhong-Sheng Wang, Tsann Lin