Abstract: A computing system has a processing device (e.g., CPU, FPGA, or GPU) and memory regions (e.g., in a DRAM device) used by the processing device during normal operation. The computing system is configured to: monitor use of the memory regions in volatile memory; based on monitoring the use of the memory regions, identify at least one of the memory regions of the volatile memory; initiate a hibernation process; and during the hibernation process, copy data stored in the identified memory regions to non-volatile memory.

Abstract: Embodiments herein provide an ultrasonic treatment device that includes a transducer holder to hold an ultrasonic transducer. The transducer holder includes multiple mounting positions for the ultrasonic transducer to enable the transducer to be held by the transducer holder at different angles. For example, in some embodiments, the transducer holder may include multiple mounting elements on an interior surface of the transducer holder. The mounting elements may be, for example, ridges or grooves on the interior surface. The transducer may include and/or be provided with one or more locking elements that interact with the mounting elements of the transducer holder to hold the transducer within the transducer holder. Other embodiments may be described and claimed.

Abstract: A computer includes: a memristor array including memristors arranged at intersections between word lines and a first bit line in the memristor array and at intersections between the word lines and second bit lines in the memristor array; an adder circuit configured to obtain sum voltages for the second bit lines by adding first voltages generated according to currents that flow in the second bit lines when a first pattern is supplied to the word lines to difference voltages between a reference voltage generated according to a current that flows in the first bit line when a second pattern is supplied to the word lines and second voltages generated according to currents that flow in the second bit lines when a second pattern is supplied to the word lines; and a detection circuit that detects a second bit line that corresponds to a maximum value of the sum voltages.

Abstract: An implantable device has a body that is substantially rigid and has an imageable shape. The body is further bioabsorbable and may contain permanent metallic elements to aid in its imaging. When the device is implanted in a resected cavity in soft tissue, it can cause the cavity to conform substantially to a known imageable shape. The implantable device is further imageable due to its attenuation properties being different from those of soft tissue such that the boundaries of the tissue corresponding to the predetermined shape can be determined.

Abstract: A phase-change memory device column decoder is divided into two portions that can be governed independently of one another, and the driving signals of the two portions are configured so as to guarantee comparable capacitive loads at the two inputs of a sense amplifier in both of the operations of single-ended reading and double-ended reading. In particular, during single-ended reading, the sense amplifier has a first input that receives a capacitive load corresponding to the direct memory cell selected, and a second input that receives a capacitive load associated to a non-selected complementary memory cell.

Abstract: There are provided a memory device for improving performance by decreasing a time at which a program operation is completed while decreasing a peak current flowing through a bit line, and an operating method of the memory device.

Abstract: A catheter system for ablation of tissue around a blood vessel, e.g., the pulmonary artery, to reduce neural activity of nerves surrounding the blood vessel. The catheter system includes an elongate shaft having a proximal portion coupled to a handle, and a distal portion. The distal portion includes a transducer and an expandable anchor, which may be actuated to transition between a collapsed delivery state and an expanded deployed state where the anchor centralizes the transducer within the blood vessel. The transducer may be actuated to emit energy to reduce neural activity of the nerves surrounding the blood vessel. Systems and method are further provided for confirming that neural activity of the nerves surround the blood vessel has been sufficiently reduced.

Abstract: A memory controller that controls a memory device including a memory block includes an initial program controller configured to control the memory device to program at least one or more monitoring memory cells from among memory cells respectively connected to monitoring word lines from among a plurality of word lines connected to the memory block, a pre-read controller configured to generate a shifting information of a threshold voltage distribution of the monitoring memory cells based on a result of reading the monitoring memory cells before a read operation is performed on the memory block, and a pre-program controller configured to control the memory device to perform the read operation after applying a pre-program voltage having a voltage level determined according to the shifting information to the plurality of word lines.

Abstract: According to one embodiment, there is provided a nonvolatile semiconductor memory device including a cell array. The cell array includes an array of a plurality of string blocks. Among the plurality of local string blocks, one local string block includes a block selection transistor and remaining local string blocks do not include a block selection transistor. A gate terminal of the block selection transistor of the one local string block is connected to a block selection line. Signals of two word lines connected to two adjacent string blocks in the bit line direction are common signals. Signals of two block selection lines connected to the two adjacent string blocks are independent of each other.

Abstract: An apparatus having an implantable ultrasound generating treating device to induce brain disorder treatment, suitable for implantation in or under the skull bone of a patient, includes several ultrasound generating transducers, which are connectable by a common electrical connection circuit to a generator, and wherein the ultrasound generating transducers each have one or several operating frequencies. The transducers include the group of transducers having several transducers driven by a same electrical drive signal, and connected to the generator system by a common electrical connection circuit, where the electric drive signal serves both as power signal and as a control signal for operating selectively, within said group, at least one or the other of a first transducer or sub-group of transducers, and of a second transducer or sub-group of transducers. The apparatus is also used to treat brain disorders.

Abstract: A storage device includes a memory cell array in which a plurality of memory cells respectively including a variable resistance memory element are divided into a plurality of memory blocks, the plurality of memory cells including a first memory cell and a second memory cell that are in the same memory block, and a detection circuit. During a read operation in which the first memory cell is a read target, the detection circuit compares a first resistance value, which is a resistance value of the variable resistance memory element in the first memory cell, with a second resistance value, which is a resistance value of the variable resistance memory element in the second memory cell, and determines a value of data stored in the first memory cell based on whether or not the first resistance value is higher or lower than the second resistance value.

Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.

Abstract: The present technology relates to a memory device and a method of operating the memory device. The memory device includes a memory block including a plurality of memory cells, and a peripheral circuit configured to perform a read operation and a dummy read operation on the memory block. A discharge slope of a pass voltage applied to the memory block during the read operation is greater than a discharge slope of a dummy pass voltage applied to the memory block during the dummy read operation.

Abstract: According to a certain embodiment, the nonvolatile semiconductor memory device includes: a memory cell array including a plurality of selected blocks and a plurality of non-selected blocks; and a row decoder including a block decoder configured to switch between the selected block and the non-selected block. The row decoder switches a block determined to be a defective block to a non-selected block and switches a block determined not to be a defective block to a selected block, on the basis of the multi-level data. The block decoder includes a defective block flag circuit including a plurality of latch circuits configured to store multi-level data.

Abstract: A read method and a write method for a memory circuit are provided, wherein the memory circuit includes a memory cell and a selector electrically coupled to the memory cell. The read method includes applying a first voltage to the selector, wherein a first voltage level of the first voltage is larger than a voltage threshold corresponding to the selector; and applying, after the applying of the first voltage, a second voltage to the selector to sense one or more bit values stored in the memory cell, wherein a second voltage level of the second voltage is constant and smaller than the voltage threshold, wherein a first duration of the applying of the first voltage is smaller than a second duration of the applying of the second voltage, wherein the second voltage is applied following the end of the first duration.

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

Abstract: A wearable ultrasound device and method of using the device includes a power controller with a power source and at least one integrated circuit that delivers electrical power to an applicator. The applicator is electrically coupled to the power controller and a surface of the applicator transmits ultrasound to a wearer for a given duration. The applicator includes radio frequency (RF) drive electronics, an ultrasound transducer coupled to the drive electronics, a monitoring apparatus that includes a thermal cutoff coupled to the drive electronics, where the monitoring apparatus monitors a temperature of the applicator surface and the thermal cutoff turns off the applicator, if the temperature exceeds a pre-defined threshold, and a coupling bandage coupled to the applicator, where the bandage positions the surface of the applicator proximate to a wearer at a location on the body of a wearer.

Abstract: A nonvolatile memory device of an embodiment includes: a first wiring line extending in a first direction; a second wiring line extending in a second direction intersecting the first direction; a memory cell disposed between the first layer and the second layer, and has first and second terminals, the memory cell including a variable resistance element; a first drive circuit capable of supplying a first potential and a second potential lower than the first potential; a second drive circuit supplying a third potential having a different polarity from a polarity of the first potential; a third drive circuit capable of supplying the second potential and a fourth potential higher than the second potential; a fourth drive circuit supplying a fifth potential having a different polarity from a polarity of the first potential; and a control circuit electrically connected to the first to fourth drive circuits.

Abstract: Disclosed are methods of obtaining zero vergence ultrasound waves for providing sonodynamic therapy with ultrasound waves. The method includes coupling a sonodynamic therapy device with an array of flat piezoelectric transducers to a skin surface. A controller is configured to generate an electrical drive signal at a frequency, modulate the drive signal, and drive the transducer with the modulated drive signal at the frequency to produce a zero vergence ultrasound wave to produce an average acoustic intensity sufficient to activate a sonosensitizer in a treatment region without damaging healthy cells in the treatment region.

Abstract: A circuit includes a first transistor and a second transistor cross-coupled with each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to a drain of the first transistor at a second node. The circuit can provide a first level of a word line voltage to the memory cell by directly coupling the power supply configured at a first level to the memory cell through the second transistor and a third transistor, and provide a second level of the word line voltage by directly coupling the power supply configured at a second level to the memory cell through the second transistor and the third transistor.