Abstract: A method of storing a data into a memory storage having bit cells. The method includes identifying each of the binary one and the binary zero in the data as either a majority bit value or a minority bit value based on the probability of finding the binary one in the data or based on the probability of finding the binary zero in the data. In the method, a bit of the data is stored into the bit cell as the more preferred state if the bit of the data has the majority bit value, and a bit of the data is stored into the bit cell as the less preferred state if the bit of the data has the minority bit value.

Abstract: A memory device includes a bit line (BL); a source line (SL); and a plurality of non-volatile memory cells operatively coupled between the BL and SL, respectively. Each of the plurality of non-volatile memory cells includes a resistor with a variable resistance, a first transistor, and a second transistor that are coupled to each other in series. In response to a first one of the non-volatile memory cell not being read and a second one of the non-volatile memory cell being read, a voltage level at a first node connected between the first and second transistors of the first non-volatile memory cell is greater than zero.

Abstract: Ultrasound-based estimation of disease activity, such as for NAS or other activity index for NAFLD for liver disease, is provided. Ultrasound measures acoustic scatter and shear wave propagation parameters, such as measuring acoustic backscatter coefficient, shear wave velocity, and shear wave damping ratio. A score for the disease activity is determined from these scatter and shear wave propagation parameters. The physician may be assisted by relatively inexpensive and rapid ultrasound as compared to biopsy or MRI based scoring in scoring activity of a disease, such as NAFLD. Ultrasound imaging is more readily available and less expensive and MRI, and is non-invasive.

Abstract: Provided is a method for estimating a pulse rate with high accuracy in the case that short-term burst noise is mixed in an estimation interval. Included are a pulse wave signal generating step of generating a pulse wave signal from an image of a pulse rate estimation target; a peak component suppression step of limiting an amplitude value of the pulse wave signal that is larger than a first threshold value to the first threshold value, and outputting a pulse wave analysis signal; and a frequency analysis step of outputting a frequency spectrum of the pulse wave analysis signal.

Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gate passage of the word line signals to the second word lines for the second sub-array in response to assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the array of memory cells, and asserts the maximum value signal if the mathematical operation performed on the less significant bits of data from the first sub-array produces a maximum data value.

Abstract: A method includes setting a current level of a write signal to a first non-zero value for a first period of time. The write signal is provided to a memory element during the first period of time. The current level of the write signal is adjusted from the first non-zero value to a second non-zero value, different from the first non-zero value, for a second period of time. The write signal is provided to the memory element during the second period of time. The current level of the write signal is adjusted from the second non-zero value to a third value, different from the first non-zero value and different from the second non-zero value, for a third period of time. The write signal is provided to the memory element during the third period of time.

Abstract: A semiconductor storage device capable of achieving low power and high integration is provided. A non-volatile semiconductor memory of the disclosure includes a memory cell array. The memory cell array has a NOR array with a NOR flash memory structure and a variable resistance array with a variable resistance memory structure formed on a substrate. An entry gate is formed between the NOR array and the variable resistance array. When the NOR array is accessed, the entry gate separates the variable resistance array from the NOR array.

Abstract: A magnetic memory includes a first spin-orbital-transfer-spin-torque-transfer (SOT-STT) hybrid magnetic device disposed over a substrate, a second SOT-STT hybrid magnetic device disposed over the substrate, and a SOT conductive layer connected to the first and second SOT-STT hybrid magnetic devices. Each of the first and second SOT-STT hybrid magnetic devices includes a first magnetic layer, as a magnetic free layer, a spacer layer disposed under the first magnetic layer, and a second magnetic layer, as a magnetic reference layer, disposed under the spacer layer. The SOT conductive layer is disposed over the first magnetic layer of each of the first and second SOT-STT hybrid magnetic devices.

Abstract: Embodiments provide a wordline driver circuit and a memory. The wordline driver circuit at least includes a first type of wordline drivers and a second type of wordline drivers, wherein each of the wordline drivers includes a PMOS transistor and an NMOS transistor. A first type of PMOS transistors in the first type of wordline drivers and a second type of PMOS transistors in the second type of wordline drivers are configured to receive different first control signals. The first type of PMOS transistors and the second type of PMOS transistors are arranged side by side, a part of the NMOS transistors in the first type of wordline drivers and the second type of wordline drivers are positioned on a side of the first type of PMOS transistors and the second type of PMOS transistors.

Abstract: Disclosed herein are related to a memory array. In one aspect, the memory array includes a set of resistive storage circuits including a first subset of resistive storage circuits connected between a first local line and a second local line in parallel. The first local line and the second local line may extend along a first direction. In one aspect, for each resistive storage circuit of the first subset of resistive storage circuits, current injected at a first common entry point of the first local line exits through a first common exit point of the second local line, such that each resistive storage circuit of the first subset of resistive storage circuits may have same or substantial equal resistive loading.

Abstract: A computing system has a processing device (e.g., CPU, FPGA, or GPU) and memory regions (e.g., in a DRAM device) used by the processing device during normal operation. The computing system is configured to: monitor use of the memory regions in volatile memory; based on monitoring the use of the memory regions, identify at least one of the memory regions of the volatile memory; initiate a hibernation process; and during the hibernation process, copy data stored in the identified memory regions to non-volatile memory.

Abstract: A computing-in-memory circuitry includes multiple digital-to-analog converters, multiple computing arrays, and multiple charge processing networks. The digital-to-analog converters convert external data into input data and the digital-to-analog converters are connected in series with a corresponding plurality of output capacitor pairs. The computing arrays receive the input data from both ends and execute a computation to output a first computing value. The charge processing networks receive and accumulate the first computing values over a predetermined time interval through switching pairs in series with the output capacitor pairs. The charge processing networks evenly distribute charges of the first computing value to selected output capacitor pairs and compare voltage differences between two ends of the output capacitor pairs to output a second computing value.

Abstract: A device for providing hyperthermia treatment includes an ultrasound energy generator configured to apply low intensity ultrasound to target tissue. The low intensity ultrasound energy induces therapeutic heating in the tissue at or below the surface of the skin. In order to control the temperature of the tissue during therapy, a microwave radiometer, such as a Dicke radiometer, can be used to measure the temperature of the tissue and feed back the temperature measurement to the ultrasound energy generator to control ultrasonic energy produced and control the temperature of the target tissue.

Abstract: The present invention provides a method for reading a current for processing analog information in a memory array for a synaptic device. To this end, the present invention provides a method for reading a memory array including a two-terminal switching material, including (a) selecting at least one cell by applying a voltage to the memory array and (b) simultaneously measuring the sum of currents from the at least one cell selected. The voltage applied to the at least one cell selected in operation (a) is higher than a voltage applied to at least one cell not selected while being within a range in which all of the selected at least one cell is not turned on.

Abstract: The present disclosure discloses an array-type ultrasound therapy system. The ultrasound therapy system includes an ultrasound therapy control unit, an ultrasound transducer driving array, and an ultrasound transducer array. The ultrasound transducer array includes n ultrasound transducers; and a detection signal output end of the ultrasound transducer configured to detect ultrasound echoes generated during ultrasound therapy is connected to a feedback signal input end of the ultrasound therapy control unit. A control signal output end of the ultrasound therapy control unit is connected to an input end of the ultrasound transducer driving array, and an output end of the ultrasound transducer driving array is connected to a driving end of each of the ultrasound transducers configured to perform the ultrasound therapy.

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings that are divided into a plurality of stacks disposed in the vertical direction, and each of the plurality of stacks includes at least one dummy word-line. The control circuit controls a program operation by applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period and by reducing a voltage level of a dummy voltage applied to the at least one dummy word-line of at least one upper stack from among the plurality of stacks during the program execution period. The at least one upper stack is disposed at a higher position than a selected stack in the vertical direction and the selected stack from among the plurality of stacks includes the selected word-line.

Abstract: An optical vital signs sensor is provided which comprises a PPG sensor (100), a pre-processing unit (130) which adapts the sampling rate or the number of pulses per sample, a processing unit (140) which executes at least one processing algorithm based on an output signal of the pre-processing unit and a sensor control unit (150). The sensor control unit is configured to control the PPG sensor by adapting the sampling rate and/or the number of pulses per sample.

Abstract: Disclosed are methods of producing randomized ultrasound waves for providing sonodynamic therapy. The method includes coupling a sonodynamic therapy device with an array of piezoelectric transducer elements to a skin surface. A controller is configured to generate an electrical drive signal to produce ultrasound waves to activate a sonosensitizer in a treatment region without damaging healthy cells in the treatment region.

Abstract: A nonvolatile memory includes a first memory cell and a second memory cell above the first memory cell. The first memory cell includes a variable resistance layer extending in a first direction, a semiconductor layer extending in the first direction and in contact with the variable resistance layer, an insulator layer extending in the first direction and in contact with the semiconductor layer, and a first voltage applying electrode extending in a second direction and in contact with the insulator layer. The second memory cell includes a second voltage applying electrode in contact with the insulator layer. When a write operation is performed on the first memory cell, a first voltage is applied to the second voltage applying electrode, and when a write operation is performed on the second memory cell, a second voltage, lower than the first voltage, is applied to the first voltage applying electrode.