Patents Examined by Hiep Nguyen
  • Patent number: 10146737
    Abstract: Methods and apparatus are disclosed for using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode logic to decode a scatter/gather instruction and generate a set of micro-operations, and an index array to hold a set of indices and a corresponding set of mask elements. A finite state machine facilitates the gather operation. Address generation logic generates an address from an index of the set of indices for at least each of the corresponding mask elements having a first value. An address is accessed to load a corresponding data element if the mask element had the first value. The data element is written at an in-register position in a destination vector register according to a respective in-register position the index. Values of corresponding mask elements are changed from the first value to a second value responsive to completion of their respective loads.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: December 4, 2018
    Assignee: Intel Corporation
    Inventors: Zeev Sperber, Robert Valentine, Guy Patkin, Stanislav Shwartsman, Shlomo Raikin, Igor Yanover, Gal Ofir
  • Patent number: 10140059
    Abstract: A memory system includes a semiconductor memory device including a plurality of memory cells, and a memory controller. The semiconductor memory device includes first, second, and third caches for storing data before the data are written into the memory cells. The memory controller is configured to issue commands to the semiconductor memory device, the commands including a first command issued with write data to store the write data in the first cache and a second command issued with write data to store the write data in the first cache and then transfer the write data in the first cache to one of the second and third caches.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: November 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Naoya Tokiwa
  • Patent number: 10133514
    Abstract: Writing data to storage utilizing a diverged thread for asynchronous write operations is provided. On a first thread, an analysis engine analyzes and identifies changed information to write to storage and an I/O manager copies the writes into buffers and places the buffers into a queue, while on a second thread, a flushless transactional layer (FTL) drive executes the writes to storage. By allowing the analysis to continue and enqueue writes on a first thread while the writes are written to storage on a second thread, the CPU and I/O of the system are utilized in parallel. Accordingly, efficiency of the computing device is improved.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: November 20, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Marcus Eduardo Markiewicz
  • Patent number: 10133667
    Abstract: Techniques related to efficient data storage and retrieval using a heterogeneous main memory are disclosed. A database includes a set of persistent format (PF) data that is stored on persistent storage in a persistent format. The database is maintained on the persistent storage and is accessible to a database server. The database server converts the set of PF data to sets of mirror format (MF) data and stores the MF data in a hierarchy of random-access memories (RAMs). Each RAM in the hierarchy has an associated latency that is different from a latency associated with any other RAM in the hierarchy. Storing the sets of MF data in the hierarchy of RAMs includes (1) selecting, based on one or more criteria, a respective RAM in the hierarchy to store each set of MF data and (2) storing said each set of MF data in the respective RAM.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: November 20, 2018
    Assignee: Orcle International Corporation
    Inventors: Niloy Mukherjee, Tirthankar Lahiri, Juan R. Loaiza, Jesse Kamp, Prashant Gaharwar, Hariharan Lakshmanan, Dhruvil Shah
  • Patent number: 10128871
    Abstract: A quarter product code codeword includes various R code symbols and C code symbols each including a plurality of symbols. Each symbol is loaded into a diagonal anti-diagonal structure in two unique locations. To provide for fast loading, the symbols may be shifted by one or more shift registers associated with the diagonal or anti-diagonal structure. The two locations at which each symbol is positioned are included within different diagonals or anti-diagonals making it possible to load or unload either symbol or multiple symbols in a single clock cycle. Further, by partitioning the diagonal anti-diagonal structure, multiple respective symbols or plurality of symbols may be loaded or unloaded in a single clock cycle.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Tobias Blaettler, Charles J. Camp, Thomas Mittelholzer, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis
  • Patent number: 10126981
    Abstract: A write command is received to store data in a Data Storage Device (DSD). At least one of a Non-Volatile Random Access Memory (NVRAM) and a Storage Class Memory (SCM) is selected for storing the data of the write command based on a number of previously received write commands indicating an address of the write command or a priority of the write command. The SCM has at least one characteristic of being faster than the NVRAM in storing data, using less power to store data, and providing a greater usable life for repeatedly storing data in a same memory location. In one example, at least a portion of the SCM is allocated for use by a host. Logical addresses assigned to the SCM are mapped to device addresses of the NVRAM. The host is provided with an indication of the logical addresses assigned to the SCM.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: November 13, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: James N. Malina, Albert H. Chen, Takeaki Kato
  • Patent number: 10102139
    Abstract: A method of operation of a host data processing system which provides a virtual operating environment for one or more guest data processing systems comprises: initiating a transaction for translation of a guest system memory address to a host system physical address in response to a transaction request from a device overseen by a guest system for access to system memory at that guest system memory address; storing identification information relating to that transaction including at least data identifying device which requested the transaction; detecting a translation error condition in respect of that transaction; and handling a detected error condition by: (i) providing information indicative of the translation error condition to the guest system overseeing the device which requested the transaction; (ii) receiving a command from the guest system in respect of that transaction, the command from the guest system comprising information identifying the device which requested the transaction; and (iii) validatin
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: October 16, 2018
    Assignee: ARM Limited
    Inventors: Matthew Lucien Evans, Stanislaw Czerniawski
  • Patent number: 10102143
    Abstract: A data processing system 2 includes an address translation cache 12 to store a plurality of address translation entries. Eviction control circuitry 10 selects a victim entry for eviction from address translation cache 12 using an eviction control parameter. The address translation cache 12 can store multiple different types of entry corresponding to respective different levels of address translation within a multiple-level page table walk. The different types of entry have different eviction control parameters assigned at the time of allocation. Eviction from the address translation cache is dependent upon the entry type, as well as the subsequent accesses to the entry concerned and the other entries within the address translation cache.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: October 16, 2018
    Assignee: ARM Limited
    Inventors: Barry Duane Williamson, Michael Filippo, . Abhishek Raja, Adrian Montero, Miles Robert Dooley
  • Patent number: 10078519
    Abstract: An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: September 18, 2018
    Assignee: Intel Corporation
    Inventors: Eliezer Weissmann, Karthikeyan Karthik Vaithianathan, Yoav Zach, Boris Ginzburg, Ronny Ronen
  • Patent number: 10055151
    Abstract: A data storage device comprises an array of data storage elements arranged as multiple partitions each comprising two or more data storage elements, each data storage element being associated with a respective identifier which identifies a data item currently stored by that data storage element; a predictor configured to compare, for each partition, information derived from the identifiers associated with the data storage elements of that partition with information derived from an identifier associated with the required data item, to identify a subset of partitions that do not store the required data item; and a comparator configured to compare identifiers associated with data storage elements of one or more partitions with the identifier associated with the required data item, wherein any partitions in the subset of partitions are excluded from the test group of partitions.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: August 21, 2018
    Assignee: ARM Limited
    Inventors: Roko Grubisic, Häkan Lars-Göran Persson, Georgia Kouveli
  • Patent number: 10049055
    Abstract: Some implementations provide a method for managing data in a storage system that includes a persistent storage device and a non-volatile random access memory (NVRAM) cache device. The method includes: accessing a direct mapping between a logical address associated with data stored on the persistent storage device and a physical address on the NVRAM cache device; receiving, from a host computing device coupled to the storage system, a request to access a particular unit of data stored on the persistent storage device; using the direct mapping as a basis between the logical address associated with the data stored on the persistent storage device and the physical address on the NVRAM cache device to determine whether the particular unit of data being requested is present on the NVRAM cache device.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: August 14, 2018
    Assignee: VIRIDIENT SYSTEMS, INC
    Inventors: Shibabrata Mondal, Vijay Karamcheti, Ankur Arora, Ajit Yagaty
  • Patent number: 10049039
    Abstract: A memory system may include: a memory device including a plurality of pages each having a plurality of memory cells coupled to a plurality of word lines and suitable for storing read data and write data requested from a host, and a plurality of memory blocks each having the pages; and a controller suitable for grouping the pages included in the memory blocks so as to divide each of the memory blocks into a plurality of page zones, and storing data corresponding to a write command into pages of a second memory block of the memory blocks and storing program update information on a first page zone of a first memory block of the memory blocks into a list, when receiving the write command for data stored in a first page of the first page zone in the first memory block.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: August 14, 2018
    Assignee: SK Hynix Inc.
    Inventor: Eu-Joon Byun
  • Patent number: 10037274
    Abstract: A method, information processing system, and computer readable storage medium, vary a maximum heap memory size for one application of a plurality of applications based on monitoring garbage collection activity levels for the plurality of applications, each application including a heap memory, and unused memory in the heap memory being reclaimed by a garbage collector.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: Norman Bobroff, Arun Iyengar, Peter Westerink
  • Patent number: 10019174
    Abstract: A storage device may be configured to determine a delay associated with execution of a read operation responsive to a read command for data stored at the storage device. The storage device may send a notification that indicates the delay, that includes data that indicates a duration of the delay, or both. In response to receiving the notification, an access device may be configured to generate a second read command for redundant associated with data stored at the storage device.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: July 10, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Brian Walter O'Krafka, Johann George, Akshay Mathur
  • Patent number: 10019191
    Abstract: A method and system for handling a file operation directed to an original file of a protected layer. A protected layer and a user- or device-specific write layer associated with the protected layer are both mounted. File open operations directed to an original file on the protected layer are instead redirected to one of a dummy file associated with the original file or a write-layer copy of the original file located on the write layer. If neither a dummy file nor a write-layer copy of the original file are on the write layer, a dummy file having the same file name and file attributes as the original file is created in the write layer. Subsequent file operations, such as reading, writing, and closing, are directed to the one of the dummy file or the write-layer copy.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 10, 2018
    Assignee: Dell Products L.P.
    Inventors: Rushikesh P. Patil, Puneet Kaushik, Satya Mylvara
  • Patent number: 10013501
    Abstract: Techniques are disclosed relating to caching web application data. In some embodiments, a computing system maintains a multi-tenant database and an in-memory cache for the database. In some embodiments, the computing system is configured to store data in an entry in response to a store request and retrieve data in response to a read request. In various embodiments, data cached by one tenant is not visible to other tenants. The cache may be partitioned and each partition may have an assigned capacity. The computing system may be configured to evict cached data based on capacity thresholds, least-recently-used information, time-to-live information, amount of data in an entry, etc. The cache may indicate misses when requested data is not present. Various disclosed techniques may improve web application performance while maintaining privacy between tenants.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: July 3, 2018
    Assignee: salesforce.com, inc.
    Inventors: Barathkumar Sundaravaradan, Christopher James Wall, Lawrence Thomas Lopez, Paul Sydell, Sreeram Duvur, Vijayanth Devadhar
  • Patent number: 10013350
    Abstract: A data storage device includes a plurality of logical regions that form n number of logical zones, each including k number of logical regions, wherein the plurality of logical regions are grouped into k number of logical region groups based on their offset values; and a processor suitable for, when receiving a write request for a target logical region, increasing a first access count stored in a first entry of a first table, corresponding to a logical zone including the target logical region, and increasing a second access count stored in a second entry of a second table, corresponding to a logical region group including the target logical region.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: July 3, 2018
    Assignee: SK Hynix Inc.
    Inventor: Se Hyun Kim
  • Patent number: 10013189
    Abstract: An apparatus comprises at least one host device for hosting respective tenants of a multi-tenant environment. The apparatus further comprises a storage platform coupled to the host device and implementing storage resources for utilization by respective tenants, and a storage controller associated with the host device comprising a storage volume creation functionality and a storage volume backup functionality. The storage volume creation functionality is configured to provision portions of the storage resources to create at least one storage volume. The storage volume backup functionality is configured to provision portions of the storage resources for performing one or more respective storage volume backup or restore processes, wherein a container is respectively provisioned for each storage volume backup or restore process.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: July 3, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Xing Yang, Kenneth Durazzo
  • Patent number: 10002077
    Abstract: According to an example, PM controller based atomicity assurance may include receiving data that is related to an application for storage in a PM. PM controller based atomicity assurance may further include receiving an indication of an atomic transaction that is related to the data, and receiving an indication to generate a CP that is related to the atomic transaction. The CP may be generated in a PM staging area. A determination may be made as to whether the CP in the PM staging area is closed or open. In response to a determination that the CP in the PM staging area is closed, content related to the CP may be propagated to the PM.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: June 19, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Boris Zuckerman, Vitaly M. Oratovsky, Douglas L. Voigt, Harold Woods
  • Patent number: 9996299
    Abstract: A data storage device may be configured to write first data to a first set of storage elements of a non-volatile memory and to write second data to a second set of storage elements of the non-volatile memory. The first data may be processed by a data shaping operation, and the second data may not be processed by the data shaping operation. The data storage device may be further configured to read a representation of the second data from the second set of storage cells and to determine a block health metric of a portion of the non-volatile memory based on the representation of the second data. The portion may include the first set of storage elements and the second set of storage elements. As an illustrative, non-limiting example, the first portion may be a first block of the non-volatile memory.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: June 12, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC
    Inventors: Nian Niles Yang, Idan Alrod