Abstract: While in active state, a first storage apparatus including first and second storage areas copies data stored in the first storage area to the second storage area, copies data stored in the first storage area to a third storage area so that data is synchronized between the first and third storage areas, and copies data stored in the second storage area to a fourth storage area so that data is synchronized between the second and fourth storage areas. When a second storage apparatus including the third and fourth storage areas has transitioned from standby to active state and thereby gets to receive access to the third storage area, instead of to the first storage area, from an external information processing apparatus, the second storage apparatus copies data stored in the third storage area to the fourth storage area, based on setting information stored in a storage unit.

Abstract: A method for authorizing I/O (input/output) commands in a storage cluster is provided. The method includes generating a token responsive to an authority initiating an I/O command, wherein the token is specific to assignment of the authority and a storage node of the storage cluster. The method includes verifying the I/O command using the token, wherein the token includes a signature confirming validity of the token and wherein the token is revocable.

Abstract: A method, information processing system, and computer readable storage medium, vary a maximum heap memory size for one application of a plurality of applications based on monitoring garbage collection activity levels for the plurality of applications, each application including a heap memory, and unused memory in the heap memory being reclaimed by a garbage collector.

Abstract: The time required for recalling the file is reduced when the file is written in a mounted plurality of tapes in comparison to recalling the file when written in a non-mounted plurality of tapes. In the non-mounted state, criteria does not typically exist in order to recall the written file within the plurality of tapes. Embodiments of the present invention provide systems and methods for recalling files based on criteria which considers: the mounted state of a tape; the type of tape; the type of available tape drive; the number of files included in a tape; and the location of the written file in a tape.

Abstract: A method, a system and an apparatus for predicting abnormalities are provided. A controller analyzes a plurality of command logs to obtain a predictive rule for accessing a storage device. The controller performs an anomaly detection for the command logs based on the predictive rule so as to obtain at least one command cluster. The controller establishes policy data corresponding to the predictive rule based on the command logs included in each command cluster, and sends the policy data to a data transmission interface coupled to the storage device. The data transmission interface obtains a processing action for a received data access command according to the policy data.

Abstract: A wrist-worn device monitors movements of a user with a flexible circuit member. The flexible circuit member is fault tolerant. It may contain extra and/or redundant traces as well as the ability to store data on RAM if the flash memory fails or if some or all trace connections between the processor and flash memory fail. Data stored on the RAM may or may not contain less fidelity. Lower fidelity data may be used to alleviate issues arising if the RAM has less storage capacity than the flash memory.

Abstract: The present disclosure relates to techniques for providing data redundancy after reducing memory writes. In one example implementation according to aspects of the present disclosure, a storage system receives a storage command for providing data redundancy in accordance with a first data redundancy scheme. The storage system then implements a subsequent data redundancy in accordance with a second data redundancy scheme.

Abstract: In an embodiment, a memory controller may determine that one or more neighboring memory cells associated with a target memory cell in a memory device are to be refreshed. The controller may generate a command associated with refreshing the one or more neighboring memory cells. The controller may transfer the command from the memory controller to the memory device containing the target memory cell. The command may direct the memory device to refresh the neighboring memory cells and/or return one or more addresses associated with the neighboring memory cells.

Abstract: A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a relationship between a group of addresses being stored in the PM according to a set of instructions when executed. The memory controller is further to retrieve the relationship when accessing an address from the groups of addresses.

Abstract: A system for mapping control and user data includes a direction scanner, an address calculator, a collision detector, a buffer, and a mapper for mapping control and user data from a first memory to a second memory. The direction scanner determines the highest priority value of to a code word index. The address calculator calculates start and end addresses of the highest priority value. When an address from an address range, defined by the start and end addresses, is already mapped to other control data, the collision detector detects a collision and generates feedback data. The address calculator outputs modified start and end addresses based on the feedback data. When no collision is detected, the address calculator outputs the modified start and end addresses to the buffer. The mapper then maps the control and user data to the modified start and end addresses in the second memory.

Abstract: Writing data to storage utilizing a diverged thread for asynchronous write operations is provided. On a first thread, an analysis engine analyzes and identifies changed information to write to storage and an I/O manager copies the writes into buffers and places the buffers into a queue, while on a second thread, a flushless transactional layer (FTL) drive executes the writes to storage. By allowing the analysis to continue and enqueue writes on a first thread while the writes are written to storage on a second thread, the CPU and I/O of the system are utilized in parallel. Accordingly, efficiency of the computing device is improved.

Abstract: Predicting what content items a user finds important and sending those items to a cache on the user's device at times when doing so will not drain resources and will not result in expensive data rates. Applying a ranking function that examines recency and other content metadata associated with the user's content items stored in a synchronized content management system. Determining how much of a ranked list of content items to cache and deciding when is a good time to send content items to the local cache.

Abstract: Providing memory training of dynamic random access memory (DRAM) systems using port-to-port loopbacks, and related methods, systems, and apparatuses are disclosed. In one aspect, a first port within a DRAM system is coupled to a second port via a loopback connection. A training signal is sent to the first port from a System-on-Chip (SoC), and passed to the second port through the loopback connection. The training signal is then returned to the SoC, where it may be examined by a closed-loop training engine of the SoC. A training result corresponding to a hardware parameter may be recorded, and the process may be repeated until an optimal result for the hardware parameter is achieved at the closed-loop training engine. By using a port-to-port loopback configuration, the DRAM system parameters regarding timing, power, and other parameters associated with the DRAM system may be trained more quickly and with lower boot memory usage.

Abstract: In one embodiment, a system comprises a database operative to maintain a social graph, a leader cache layer comprising one or more leader cache clusters, and a follower cache layer comprising one or more follower cache clusters, wherein the leader cache layer is operative to, communicate social graph information between the follower cache cluster and the database, wherein each follower cache cluster maintains at least a portion of the social graph, receive a request from one of the follower cache clusters to store social graph information in the database, update the database storing the social graph responsive to the request, and update one or more of the follower cache clusters storing the portion of the social graph associated with the request.

Abstract: Provided are a method and apparatus for remapping logical to physical addresses for a non-volatile memory having dies. Bands extend through the dies and planes in the dies extending through the bands define addressable blocks. A first remapping of a logical-to-physical mapping is performed by remapping logical addresses of blocks in a first end of the bands that map to defective physical blocks to map to good physical blocks at a second end of the bands. After performing the first remapping, a second remapping of the logical-to-physical mapping is performed by remapping logical addresses in the second end of bands that map to defective blocks to map to good physical blocks in the first end of bands.

Abstract: Systems and methods for performing file-level restore operations for block-level data volumes are described. In some embodiments, the systems and methods restore data from a block-level data volume contained in secondary storage by receiving a request to restore one or more files from the block-level data volume, mounting a virtual GUID Partition Table (GPT) disk to the block-level data volume, accessing one or more mount paths established by the virtual GPT disk between the data agent and the block-level data volume, and browsing data from one or more files within the block-level data volume via the established one or more mount paths provided by the virtual GPT disk.

Abstract: When computers and virtual machines operating in the computers both attempt to allocate a cache regarding the data in a secondary storage device to respective primary storage devices, identical data is prevented from being stored independently in multiple computers or virtual machines. An integrated cache management function in the computer arbitrates which computer or virtual machine should cache the data of the secondary storage device, and when the computer or the virtual machine executes input/output of data of the secondary storage device, the computer inquires the integrated cache management function, based on which the integrated cache management function retains the cache only in a single computer, and instructs the other computers to delete the cache. Thus, it is possible to prevent identical data from being cached in a duplicated manner in multiple locations of the primary storage device, and enables efficient capacity usage of the primary storage device.

Abstract: To detect an abnormality of logical and physical addresses, a storage device includes: plural drives each having a storage medium configuring a logical volume provided to a host device; a front end I/F that receives an I/O request including a logical address for identifying a logical storage area of the logical volume, and user data from the host computer; a processor that controls conversion from the logical address into the physical address for identifying a physical storage area of the storage medium; and a back end I/F that controls write/read of user data with respect to the drives based on the physical address. In the drives, data where a first guarantee code obtained based on the physical address and the logical address corresponding to the physical address is added to the user data is stored in the physical storage area designated by the physical address of the storage medium.

Abstract: The present disclosure relates systems and methods for executing an encrypted code section in a shieldable CPU memory cache. Functional characteristics of the software product of a vendor, such as gaming or video, may be partially encrypted to allow for protected and functional operability and avoid hacking and malicious usage of non-licensed user. The encrypted instructions may be written to the CPU memory cache and decrypted only once the CPU memory cache is switched into a shielded state. The decrypted code instructions may be executed from a designated cache-line of said CPU memory cache still in the shielded state.

Abstract: A method includes, in various implementations, regulating a memory region for execute-only access, storing a set of instructions in the memory region, executing an early instruction among the set of instructions, and executing a set of subsequent instructions among the instructions. The early instruction loads a secret value into a volatile register. A correct execution of the subsequent instructions depends on the secret value being loaded into the volatile register. A system includes, in various implementations, a memory and a processor with one or more volatile registers. The processor regulates access to portions of the memory. The processor can load a secret value into the volatile register in response to executing a program stored in an execute-only portion of the memory. The processor is configured to lose, in response to an asynchronous event, information loaded in the volatile registers.