Abstract: A technique includes, in response to a first stream of writes to a first non-volatile memory system, generating a second stream of writes for a second non-volatile memory system; and coordinating replication of data stored in the first non-volatile memory system. The coordinating includes embedding at least one command in the second stream of writes to create a synchronization point for data storage in the second non-volatile memory system in response to at least one corresponding command in the first stream to create a synchronization point for data storage in the first non-volatile memory system.

Abstract: A method and system for compute element state replication is provided. The method includes transforming at least a subset of metadata of a source compute element from a memory tier of the source compute element to a block representation; within a destination compute element, mounting the block representation; reverse transforming the metadata to a memory tier of the destination compute element; and using the reverse transformed metadata to operate the destination compute element.

Abstract: The present invention discloses a method for implementing hot migration of a virtual machine. In this method, a source virtual machine migration management apparatus on a source physical machine determines non-temporary data memory pages of a virtual machine on the source physical machine, copies the non-temporary data memory pages from the source physical machine to a target physical machine, cyclically copies dirty pages, which are generated in the process of copying the non-temporary data memory pages, from the source physical machine to the target physical machine until a ratio of a quantity of dirty pages which are not yet copied to a quantity of the non-temporary data memory pages is less than a preset value; and performs migration of the virtual machine when the ratio is less than the preset value.

Abstract: The present disclosure relates to sharing a context on a coherent hardware accelerator among multiple processes. According to one embodiment, in response to a first process requesting to create a shared memory space, a system creates a shared hardware context on the coherent hardware accelerator and binds the first process and the shared memory space to the hardware context. In response to the first process spawning one or more second processes, the system binds the one or more second processes to the shared memory space and the hardware context. Subsequently, the system performs one or more operations initiated by the first process or one of the one or more second processes on the coherent hardware accelerator according to the bound hardware context.

Abstract: Provided is an electronic apparatus avoiding to be a starting failure status even if power off happens during the writing of a program. The electronic apparatus includes a rewritable nonvolatile memory, volatile memory, and a processor. The nonvolatile memory memorizes a plurality of programs. The volatile memory memorizes a plurality of programs for updating. The processor makes the plurality of programs memorize in volatile memory and writes in the plurality of programs for updating in a nonvolatile memory. In this case, in the state of reserving the start processing program and the header information before updating, a processor writes in the start processing program for updating, beforehand. Subsequently, the processor writes in the header information for updating. After that, the processor writes in the executive operation program for updating.

Abstract: A storage device comprises plural memory units and a storage controller that controls the memory units as a RAID group. Each memory unit is provided with a nonvolatile semiconductor memory (e.g. flash memory) chip and a memory controller that compresses data and stores the compressed data into the nonvolatile semiconductor memory chips. The memory controller makes a logical memory area available to the storage controller. The storage controller divides the logical memory area into plural entries each of which is a logical memory area of a prescribed size, acquires from respective memory unit capacity information on the data capacity stored into the nonvolatile semiconductor memory, and exchanges data of entries between the semiconductor memory units on the basis of the capacity information.

Abstract: A method of creating a new layer for an information handling system is disclosed. A layering client mounts a new layer at a layer storage medium accessible to the information handling system. A layering file system filter driver redirects a request to create a new file at a target file path to the layer storage medium and updates the file metadata to associate the target file path with the path to file created on the layer storage medium.

Abstract: A control apparatus with multiple flash memory card channels includes a host side port unit, an instruction data processing unit, and flash memory card port units. The host side port unit exchanges a host side instruction and host side read/write data with a high-speed serial communication protocol host side. The flash memory card port units respectively exchange flash memory card instructions and flash memory card read/write data with a plurality of flash memory cards. An instruction from the high-speed serial communication protocol host side is divided into multiple sub-instructions to be respectively transmitted to the flash memory card port units and exchange of instruction and data with a plurality of flash memory cards is carried out in a coincident period of time so as to achieve the purposes of expanding access capacity and increasing access speed, reducing the operation cost of products, and enhancing flexibility of use of flash memory cards.

Abstract: A tagged cache is disclosed for data coherency in multi-domain debug operations. Access requests to a memory within a target device are received for data views associated with debug operations, and access requests include virtual addresses associated with virtual address spaces and client identifiers associated with requesting data views. Virtual addresses are translated to physical addresses within a tagged cache using address translation tables that associate virtual addresses from the different virtual address spaces with client identifiers and with physical addresses within the cache. Data within the cache is cached using the physical addresses. Further, when data is written to the cache, virtual address tags within the cache are used to identify if other virtual addresses are associated with the physical address for the write access request. If so, client identifiers stored within the address translation tables are used to notify affected data views of changed data.

Abstract: Techniques and mechanisms to efficiently cache data based on compression of such data. The technologies of the present disclosure include cache systems, methods, and computer readable media to support operations performed with data that is compressed prior to being written as a cache line in a cache memory. In some embodiments, a cache controller determines the size of compressed data to be stored as a cache line. The cache controller identifies a logical block address (LBA) range to cache the compressed data, where such identifying is based on the size of the compressed data and on reference information describing multiple LBA ranges of the cache memory. One or more such LBA ranges are of different respective sizes. In other embodiments, LBA ranges of the cache memory concurrently store respective compressed cache lines, wherein the LBA ranges and are of different respective sizes.

Abstract: A primary write request that is to modify a primary portion of primary data stored in a primary storage node is received. The primary write request is to be replicated to create a current secondary write request. The current secondary write request is to modify a current secondary portion of secondary data that is stored in a secondary storage node. A current data range of the current secondary portion is determined. A determination is made of whether a previous secondary write request is in process of modifying a previous data range that at least partially overlaps with a current data range of the current secondary portion. Execution of the primary write request is suspended, until the previous secondary write request has completed updating the secondary storage node.

Abstract: A quarter product code codeword includes various R code symbols and C code symbols each including a plurality of symbols. Each symbol is loaded into a diagonal anti-diagonal structure in two unique locations. To provide for fast loading, the symbols may be shifted by one or more shift registers associated with the diagonal or anti-diagonal structure. The two locations at which each symbol is positioned are included within different diagonals or anti-diagonals making it possible to load or unload either symbol or multiple symbols in a single clock cycle. Further, by partitioning the diagonal anti-diagonal structure, multiple respective symbols or plurality of symbols may be loaded or unloaded in a single clock cycle.

Abstract: According to one embodiment, a storage system includes a plurality of memory units including a nonvolatile memory and a control unit which controls the nonvolatile memory, a routing unit which controls transfer of a packet between the memory units. The routing unit uses a partial address described in the packet and not the full address.

Abstract: A computer system, having: a storage apparatus having: a storage volume constructed by a physical resource; a host computer having a storage volume assigned from the storage apparatus; management computers having: a first management computer configured to manage the storage apparatus; and a second management computer configured to manage the host computer, the second management computer including: first template information for identifying a change that occurs in the host configuration information; and management subject resource relationship information, the first management computer being configured to notify, before the management operation accompanying the configuration change is carried out for the storage apparatus, the second management computer of a change that occurs in the storage configuration information, the second management computer being configured to identify the change that occurs in the host configuration information based on the change that occurs in the storage configuration information n

Abstract: In one embodiment, a node of a cluster is coupled to a storage array of storage devices. The node executes a storage input/output (I/O) stack having a redundant array of independent disks (RAID) layer that organizes the storage devices within the storage array as a plurality of RAID groups. Configuration information is stored as a cluster database. The configuration information identifies the RAID groups associated with the storage devices. Each RAID group is associated with a plurality of segments and each segment has a different RAID configuration.

Abstract: A semiconductor memory apparatus is provided. The semiconductor memory apparatus does not require additional identification information to perform data scrambling and improves the reliability, where the identification information is used to identify whether it is an erased data or a programmed data. A flash memory of the present disclosure includes a scrambling unit 120 scrambling data between an input/output buffer 110 and a page buffer 160. The scrambling unit 120 includes a writing encoder 200 and a reading decoder 220. When an input data is equal to a predetermined bit string, the writing encoder 200 skips the scrambling of the input data. When a read data of the page buffer 160 is equal to the predetermined bit string, the reading decoder 220 skips the descrambling of the read data.

Abstract: Methods and systems for managing resources in a networked storage environment are provided. One method includes generating a relationship between latency and utilization of a resource in a networked storage environment using observation based, current and historical latency and utilization data, where latency is an indicator of delay at the resource for processing any request and utilization of the resource is an indicator of an extent the resource is being used at any given time; and selecting an optimal point for the generated relationship between latency and utilization, where the optimal point is an indicator of resource utilization beyond which throughput gains for a workload is smaller than increase in latency.

Abstract: An apparatus and method are described for asynchronous tile-based rendering control. In one embodiment of the invention, there is a delay between when the graphics driver queues the GPU commands for rendering and when the GPU begins executing. During this delay, the graphics driver receives additional information or data about whether cache evictions may be inhibited. As such, it allows the graphics driver to defer the cache eviction control of its render cache until it has this extra information. By doing so, it reduces the memory bandwidth required for rendering 3D graphics applications and in turn reduces the power consumption of the GPU.

Abstract: When a failure occurs in a storage device, a backup unit specifies LUNs of a copy source and a copy destination to an operation volume for which a process is not taken over to another storage device and instructs to perform a copy. When a copy processing unit in the storage device receives a copy process to be performed in the operation volume, the copy processing unit performs the copy process by using the specified LUNs of the copy source and the copy destination. If an error occurs without the copy process being taken over to another storage device due to the occurrence of a failover, the backup unit acquires the LUNs of two volumes of a copy pair and the volumes each constituting each of cluster pairs. Then, the backup unit again performs the copy process by using the acquired LUNs.

Abstract: A method of operation in a non-volatile memory system for deferring, in accordance with a determination to reduce power consumption by the non-volatile memory system, execution of commands in a command queue corresponding to a distinct set of non-volatile memory devices during a respective wait period. In some implementations, the respective wait period for a first distinct set of non-volatile memory devices in at least two distinct sets is at least partially non-overlapping with the respective wait period for a second distinct set of non-volatile memory devices in the at least two distinct sets.