Patents Examined by Hiep Nguyen
  • Patent number: 8788777
    Abstract: A memory controller for managing data and power in a memory is described. In some implementations, the memory controller is configured to identify a first area of the memory to be operated at a first power level, identify a second area of the memory to be operated at a second power level, transfer data in a region in the second area to a region in the first area, maintain a mapping of an address associated with the region in the second area to an address associated with the region in the first area, operate the first area at the first power level, and operate the second area at the second power level.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: July 22, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Ofer Zaarur, Jason Chagas
  • Patent number: 8782330
    Abstract: A system and method for protecting boot and recovery area of a flash memory in order to meet GMR requirements in radio system is disclosed. When the Core Engine Modem is installed in the factory test equipment, LOCK signal on the PoP module is logic high. At this time, the flash will be unlocked, and the boot and recovery code is written. The boot and recovery sectors will then be locked and the user area of the flash is left unlocked. When installed in the GLS DICE-T, LOCK signal on the PoP module is logic low. At this time, the flash device will ignore block lock commands, which prevent the unlocking of the protected sectors. The write enable signal from the GVA can now be utilized to enable writing to the user area of the flash despite of protecting boot and recovery areas.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: July 15, 2014
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Boris Radovcic
  • Patent number: 8775773
    Abstract: The storage system exports logical storage volumes that are provisioned as storage objects. These storage objects are accessed on demand by connected computer systems using standard protocols, such as SCSI and NFS, through logical endpoints for the protocol traffic that are configured in the storage system. Logical storage volumes are created from a logical storage container having an address space that maps to storage locations of the physical data storage units. Each of the logical storage volumes so created has an address space that maps to the address space of the logical storage container. A logical storage container may span more than one storage system and logical storage volumes of different customers can be provisioned from the same logical storage container with appropriate security settings.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: July 8, 2014
    Assignee: VMware, Inc.
    Inventors: Sanjay Acharya, Rajesh Bhat, Satyam B. Vaghani, Ilia Sokolinski, Chiao-Chuan Shih, Komal Desai
  • Patent number: 8775774
    Abstract: The storage system exports logical storage volumes that are provisioned as storage objects. These storage objects are accessed on demand by connected computer systems using standard protocols, such as SCSI and NFS, through logical endpoints for the protocol traffic that are configured in the storage system. To facilitate creation and management of logical storage volumes, special application programming interfaces (APIs) have been developed. The special APIs include commands to create a logical storage volume, bind, unbind, and rebind the logical storage volume, extend the size of the logical storage volume, clone the logical storage volume, and move the logical storage volume.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: July 8, 2014
    Assignee: VMware, Inc.
    Inventors: Komal Desai, Satyam B. Vaghani
  • Patent number: 8775762
    Abstract: A memory controller includes a batch unit, a batch scheduler, and a memory command scheduler. The batch unit includes a plurality of source queues for receiving memory requests from a plurality of sources. Each source is associated with a selected one of the source queues. The batch unit is operable to generate batches of memory requests in the source queues. The batch scheduler is operable to select a batch from one of the source queues. The memory command scheduler is operable to receive the selected batch from the batch scheduler and issue the memory requests in the selected batch to a memory interfacing with the memory controller.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: July 8, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gabriel H. Loh, Rachata Ausavarungnirun
  • Patent number: 8769240
    Abstract: An integrated circuit includes a random address generation unit configured to generate a first random address for a data randomizing operation, an address conversion unit configured to convert the first random address and generate a second random address, and a synchronization output unit configured to sequentially output the first and second random addresses in synchronization with a clock signal.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: July 1, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dae-Il Choi
  • Patent number: 8762637
    Abstract: According to an example, a data storage apparatus may include a non-volatile primary storage medium, a coupling interface to removably receive a non-volatile solid state device, a communication line connected to the non-volatile primary storage medium and the coupling interface, and a storage controller connected to the communication line. The storage controller may determine a memory type of the non-volatile solid state device, cache a first type of data in the non-volatile solid state device in response to a determination that the non-volatile to solid state device is of a first memory type, and cache a second type of data in the non-volatile solid state device in response to a determination that the non-volatile solid state device is of a second memory type, in which the second type of data differs from the first type of data.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: June 24, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Fred Thomas, Walter A. Gaspard
  • Patent number: 8762627
    Abstract: A method and system defragments data during garbage collection. Garbage collection may be more efficient when the valid data that is aggregated together is related or logically linked. In particular, data from the same file or that is statistically correlated may be combined in the same blocks during garbage collection.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: June 24, 2014
    Assignee: SanDisk Technologies Inc.
    Inventor: Rotem Sela
  • Patent number: 8762681
    Abstract: For block based end-to-end data protection for extended count key data (ECKD) in a computing environment, information units (IU's) are aligned in a block boundary format. Block protection trailer data is added to each one of the IU's.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: June 24, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gerhard Banzhaf, Maor Ben-Dayan, Kenneth W. Boyd, Thomas Schlipf, Helmut H. Weber
  • Patent number: 8751756
    Abstract: A method of writing data in a memory system comprises determining a characteristic of write data and generating characteristic information according to the determined characteristic, generating a write command corresponding to the write data, and sending the write command, the characteristic information, and the write data to the memory system.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: June 10, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yangsup Lee, Wonmoon Cheon
  • Patent number: 8745320
    Abstract: Relatively small capacity solid-state storage devices (SSD) are combined with larger capacity magnetic disk storage devices for storing storage block write data to ensure data consistency. Write operations are stored in a sequential write buffer in an SSD to guarantee the storage of write data and then copied from the sequential write buffer to the destination address in a magnetic disk storage device. The sequential write buffer store write data in locations corresponding to the order of receipt of write operations. Write data from the sequential write buffer is transferred to the magnetic disk storage device in the same order and a checkpoint index is frequently updated to indicate the completion of some transfers. During system initialization, the most recent value of the checkpoint index is retrieved and used as a starting location for transferring write data from the sequential write buffer to the magnetic disk storage device.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: June 3, 2014
    Assignee: Riverbed Technology, Inc.
    Inventors: Nitin Gupta, Kiron Vijayasankar, Joshua Berry
  • Patent number: 8738879
    Abstract: Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: May 27, 2014
    Assignee: Conversant Intellectual Property Managament Inc.
    Inventors: Hong Beom Pyeon, Hakjune Oh, Jin-Ki Kim
  • Patent number: 8738877
    Abstract: Improved memory management in a processor is provided using garbage collection utilities. The processor includes higher performance memory units and lower performance memory units and a memory management unit. The memory management unit includes a garbage collection utility programmed to identify high use memory blocks and low use memory blocks within the higher and lower performance memory units. The memory management unit is also configured to move the high use memory blocks to higher performance memory and move the low use memory blocks to lower performance memory. The method comprises determining performance characteristics of available memory to identify higher performance memory and lower performance memory. Next memory block use metrics are analyzed to identify high use memory blocks and low use memory blocks. Finally, high use memory blocks are moved to the higher performance memory while the low use memory blocks are moved to the lower performance memory.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: May 27, 2014
    Assignee: Advance Micro Devices, Inc.
    Inventors: Gabriel H. Loh, Mauricio Breternitz
  • Patent number: 8738878
    Abstract: Methods, program products, and systems for lock-free object recycling are described. In some implementations, a system can provide a type-neutral wrapper for a first data object. Upon receiving an indicator that the first data object is no longer used, the system can store the first data object and the type-neutral wrapper in a lock-free data structure. Upon receiving a request to create a second data object, the system can fetch the type-neutral wrapper and the first data object from the lock-free data structure without using a lock. The system can then return the first data object as a response to the request.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: May 27, 2014
    Assignee: Apple Inc.
    Inventor: Wei-De Ju
  • Patent number: 8732434
    Abstract: A memory device includes a hash table storing a hash value, a bit value, and a page address for each of a plurality of pages, a memory cell unit configured to store the pages and output contents corresponding to the page addresses of the pages having a same hash value, and a controller including a comparator configured to compare the contents output from the memory cell unit and change at least one bit value associated with a respective one of the pages upon determining that the contents of the pages are the same.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: May 20, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joo Young Hwang, Hak Soo Yu
  • Patent number: 8732433
    Abstract: Apparatuses and methods for providing data are disclosed. An example apparatus includes a plurality of memories coupled to a data bus. The memories are configured to provide data to the data bus responsive, at least in part, to a first address. The plurality of memories are further configured to provide at least a portion of the data corresponding to the first address to the data bus during a sense operation for a second address provided to the plurality of memories after the first address. Each of the plurality of memories provides data to the data bus corresponding to the first address at different times. Moreover, a plurality of memories may be configured to provide at least 2N bits of data to the data bus responsive, at least in part, to an address, each of the plurality of memories configured to provide N bits of data to the data bus at different times.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: May 20, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Yi Chen, Yihua Zhang, Keith E. Winters
  • Patent number: 8725951
    Abstract: Approaches for an object store implemented, at least in part, on one or more solid state devices. The object store may store objects on a plurality of solid state devices. The object store may include a transaction model means for ensuring that the object store performs transactions in compliance with atomicity, concurrency, isolation, and durability (ACID) properties. The object store may include means for providing parallel flushing in a write cache maintained on each of the solid state devices. The object store may include means for maintaining one or more double-write buffers, for the object store, at a location other than the solid state devices. The object store may optionally comprise means for maintaining one or more circular transaction logs, for the object store, at a location other than the solid state devices. The object store may operate to minimize write operations performed on the solid state devices.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: May 13, 2014
    Assignee: Sandisk Enterprise IP LLC
    Inventors: John Busch, Darpan Dinker, Darryl Ouye
  • Patent number: 8725960
    Abstract: A storage subsystem receives writes from a computer via a storage subsystem interface. The storage subsystem reduces a number of the writes. A single drive of the storage subsystem has primary and redundant storage devices with storage device interfaces. A disk controller of the single drive implements a data redundancy scheme by storing data associated with the reduced number of writes in the primary storage devices and by storing computed redundancy information in the redundant storage devices. The disk controller is operable without a loss of data in the presence of at least a single failure of any of the storage devices. Optionally the storage devices are flash memory devices. Optionally the disk controller is operable without a loss of data in the presence of at least two failures of any of the storage devices when a number of the redundant storage devices is at least two.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: May 13, 2014
    Assignee: LSI Corporation
    Inventor: Radoslav Danilak
  • Patent number: 8713245
    Abstract: A Flash-based storage system, card, and/or module comprises a Flash controller configured to encrypt the data pages of a page stripe by shuffling the data pages, including loading each data page into a data shuffling buffer in a sequential order relative to other data pages in the page stripe, and thereafter unloading each data page in a non-sequential order relative to other data pages in the page stripe. The Flash controller is also configured to scramble the data pages of the page stripe by performing a bitwise logical operation on the data pages that are unloaded from the data shuffling buffer. A user key and one or more system keys are used to perform the shuffling and scrambling. The Flash controller is further configured to flush the user key by bypassing the system's backup power supply and performing an emergency system shutdown without backing up system data.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: April 29, 2014
    Assignee: International Business Machines Corporation
    Inventors: Holloway H. Frost, Charles J. Camp
  • Patent number: 8706981
    Abstract: An electronic communication unit which is in the form of a sensor and/or actuator unit, including at least a first status information processing module having a status memory unit which stores status information for the communication unit in the form of a status data item (stat), wherein the first status information processing module further includes a masking memory unit connected to the status memory unit and also a status processing element connected to the masking memory unit, wherein the first status information processing module is designed such that at least one status information item from the status data item (stat) is selected by the masking memory unit and the resultant selective status data item (sel-stat) is processed by the status processing element such that the output of the latter provides a short status data item (k-stat) which has a shorter data word length than the selective status data item (sel-stat).
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: April 22, 2014
    Assignee: Continental Teves AG & Co. oHG
    Inventors: Jörn Schriefer, Jürgen Scherschmidt, Thomas Peichl