Patents Examined by Hiep Nguyen
  • Storage device, control device, and control method
    Patent number: 9170747
    Abstract: A storage device includes a data division unit that divides data into data blocks, a duplicate storage determining unit that determines whether the same data block as that to be stored has been stored in a storage unit for discharge in an export process, and a data storage processing unit that stores the data block to be stored in the storage unit for discharge when the same data block has not been stored in the storage unit for discharge and prevents the data block to be stored from being stored in the storage unit for discharge when the same data block has been stored in the storage unit for discharge. According to the storage device, it is possible to reduce the amount of data stored in the storage unit for discharge.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: October 27, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Naoyoshi Toshine
  • Clustered raid assimilation management
    Patent number: 9170746
    Abstract: In one embodiment, a node is a member of a cluster having a plurality of nodes, where each node is coupled to one or more storage arrays of solid state drives (SSDs) that serve as main storage. The node executed a storage input/output (I/O) stack having a redundant array of independent disks (RAID) layer that organizes the SSDs within the one or more storage arrays as one or more RAID groups. Configuration information is stored as a cluster database. The configuration information identifies (i) one or more RAID groups associated with an extent store, (ii) SSDs within each RAID group, and (iii) an identification of a node that owns the extent store. The cluster database is stored separate and apart from the main storage.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: October 27, 2015
    Assignee: NetApp, Inc.
    Inventors: Rajesh Sundaram, Bharat Baddepudi
  • Dynamically removing entries from an executing queue
    Patent number: 9158698
    Abstract: According to an embodiment, a computer-implemented method for control block management is provided. The computer-implemented method includes placing one or more control blocks in a queue for execution by a computer hardware device. The computer-implemented method also includes allocating a purge flag in each of the control blocks. The purge flag instructs the computer hardware device to skip execution of the corresponding control block.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Cadigan, Jr., Scot H. Rider, Donald W. Schmidt
  • Dynamically allocating memory for processes
    Patent number: 9152549
    Abstract: A system, computer-readable storage medium storing at least one program, and a computer-implemented method for dynamically allocating memory for processes is presented. A first request to allocate memory for a first process is received, where the first process is associated with a first quality-of-service class in a plurality of quality-of-service classes. A first memory allocation for the first quality-of-service class is calculated as a function of a current amount of free memory on the server and a first minimum memory allocation for the first quality-of-service class. An amount of memory currently used by processes associated with the first quality-of-service class is determined. The first request is rejected when the amount of memory currently used by the processes associated with the first quality-of-service class is greater than or equal to the first memory allocation.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: October 6, 2015
    Assignee: GOOGLE INC.
    Inventor: Alex Kesselman
  • Optimizing memory usage across multiple garbage collected computer environments
    Patent number: 9146862
    Abstract: A method, information processing system, and computer readable storage medium, vary a maximum heap memory size for one application of a plurality of applications based on monitoring garbage collection activity levels for the plurality of applications, each application including a heap memory, and unused memory in the heap memory being reclaimed by a garbage collector.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: September 29, 2015
    Assignee: International Business Machines Corporation
    Inventors: Norman Bobroff, Arun Iyengar, Peter Westerink
  • Remote enabling of storage
    Patent number: 9141287
    Abstract: Techniques for enabling storage remotely are presented. A REpresentational State Transfer (REST) front-end interface is interfaced to a legacy file system via a backend interface that directly interacts with the native storage and protocols of the legacy file system. The REST interface is presented as the frontend interface to the legacy file system making the storage of the legacy file system available to web or network-enabled devices.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 22, 2015
    Assignee: Novell, Inc.
    Inventors: Scott Alan Isaacson, Jim Alan Nicolet, Nadeem Ahmad Nazeer, Bradley Garrell Nicholes, Kevin Marinus Boogert
  • Die-stacked memory device providing data translation
    Patent number: 9135185
    Abstract: A die-stacked memory device incorporates a data translation controller at one or more logic dies of the device to provide data translation services for data to be stored at, or retrieved from, the die-stacked memory device. The data translation operations implemented by the data translation controller can include compression/decompression operations, encryption/decryption operations, format translations, wear-leveling translations, data ordering operations, and the like. Due to the tight integration of the logic dies and the memory dies, the data translation controller can perform data translation operations with higher bandwidth and lower latency and power consumption compared to operations performed by devices external to the die-stacked memory device.
    Type: Grant
    Filed: December 23, 2012
    Date of Patent: September 15, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gabriel H. Loh, Bradford M. Beckmann, James M. O'Connor, Michael Ignatowski, Michael J. Schulte, Lisa R. Hsu, Nuwan S. Jayasena
  • Techniques for providing data redundancy after reducing memory writes
    Patent number: 9128872
    Abstract: A storage subsystem receives writes via a storage subsystem interface and reduces a number of the writes. Data associated with the reduced number of writes is stored in storage devices of a single drive. Computed redundancy information is stored in the storage devices. A data redundancy scheme is implemented via a disk controller that is enabled to operate without a loss of data in the presence of at least a single failure of any of the storage devices.
    Type: Grant
    Filed: May 11, 2014
    Date of Patent: September 8, 2015
    Assignee: Seagate Technology LLC
    Inventor: Radoslav Danilak
  • System and method for monitoring memory stack size
    Patent number: 9128630
    Abstract: A system and method for monitoring a memory stack size is provided, and more particularly, a method for monitoring a memory stack size, whereby the size of a memory stack applied to an operating system of a controller for a vehicle is monitored so that an overflow phenomenon of the memory stack can be prevented. That is, an accurate usage amount of a memory stack of the entire control system for a hybrid vehicle is efficiently and effectively monitored so that, when the control system reaches a risk level of stack overflow, fail-safe logic is executed and an overflow phenomenon of the memory stack as a result can be prevented.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: September 8, 2015
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Ji Yong Park, Ui Jung Jung
  • Selective cache fills in response to write misses
    Patent number: 9128856
    Abstract: A cache memory receives a request to perform a write operation. The request specifies an address. A first determination is made that the cache memory does not include a cache line corresponding to the address. A second determination is made that the address is between a previous value of a stack pointer and a current value of the stack pointer. A third determination is made that a write history indicator is set to a specified value. The write operation is performed in the cache memory without waiting for a cache fill corresponding to the address to be performed, in response to the first, second, and third determinations.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: September 8, 2015
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Mithuna Thottethodi, Yasuko Eckert, Srilatha Manne
  • Memory heaps in a memory model for a unified computing system
    Patent number: 9116809
    Abstract: A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: August 25, 2015
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Anthony Asaro, Kevin Normoyle, Mark Hummel
  • Apparatus and method of using dummy data while storing data at a multi-bit storage element
    Patent number: 9110788
    Abstract: A storage device includes a controller and a non-volatile memory that includes a three-dimensional (3D) memory. A method performed in the data storage device includes receiving, at the controller, first data and second data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, the second data, and dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The dummy data prevents a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: August 18, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Manuel Antonio D'Abreu, Dimitris Pantelakis
  • Deployment of a software image on multiple targets with streaming technique
    Patent number: 9104431
    Abstract: Deploying a software image from a source data-processing system on target data-processing entities of a target data-processing system, the software image including memory blocks being individually accessible, with a predefined subset of the memory blocks defining a bootstrap module. The deploying includes downloading the bootstrap module onto a main one of the target data-processing entities from the source data-processing system, booting the main target data-processing entity from the bootstrap module thereby loading a streaming driver in the bootstrap module, and serving each request of accessing a selected memory block of the software image on the main data-processing entity by the streaming driver.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jacques Fontignie, Claudio Marinelli, Bernardo Pastorelli, Luigi Pichetti
  • Two stage checksummed raid storage model
    Patent number: 9104342
    Abstract: A method for writing a logical data block to storage. The method includes receiving a request to write a logical data block to a storage pool, allocating a number of physical log blocks in a RAID log and a parity block for the logical data block, and writing the logical data block and the parity block to the physical log blocks. The number of the physical log blocks are less than a number of disks storing the RAID log. The method further includes allocating space in a physical slab block in a RAID slab for the logical data block, copying data including the logical data block to the space in the physical slab block, and updating, in the RAID slab, a checksum corresponding to the physical slab block and a parity block that includes the data stripe having the physical slab block based on the data copied.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: August 11, 2015
    Assignee: Oracle International Corporation
    Inventors: Roch Bourbonnais, Blaise Sanouillet
  • System, method, and computer program product for implementing a storage array
    Patent number: 9093135
    Abstract: A system, method, and computer program product are provided for implementing a storage array. In use, a storage array is implemented utilizing static random-access memory (SRAM). Additionally, the storage array is utilized in a multithreaded architecture.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: July 28, 2015
    Assignee: NVIDIA Corporation
    Inventors: Brucek Kurdo Khailany, James David Balfour, Ronny Meir Krashinsky
  • Hybrid cache
    Patent number: 9087561
    Abstract: Data caching methods and systems are provided. A method is provided for a hybrid cache system that dynamically changes modes of one or more cache rows of a cache between an un-split mode having a first tag field and a first data field to a split mode having a second tag field, a second data field being smaller than the first data field and a mapped page field to improve the cache access efficiency of a workflow being executed in a processor. A hybrid cache system is provided in which the cache is configured to operate one or more cache rows in an un-split mode or in a split mode. The system is configured to dynamically change modes of the cache rows from the un-split mode to the split mode to improve the cache access efficiency of a workflow being executed by the processor.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 21, 2015
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Matthew R. Poremba, Gabriel H. Loh
  • Two-level system main memory
    Patent number: 9087584
    Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: July 21, 2015
    Assignee: Intel Corporation
    Inventors: Eric J. Dahlen, Glenn J. Hinton, Raj K. Ramanujan
  • Elastic I/O processing workflows in heterogeneous volumes
    Patent number: 9081683
    Abstract: The present disclosure provides advantageous methods and systems for input/output processing workflows in a heterogeneous data volume. One embodiment relates to a method of writing data to a heterogeneous data volume having multiple disk classes of storage. A class of storage tier for the data write is selected using operating modes for the tiers, where the operating mode for a tier instance depends on statistical measures of operating parameters for that tier. One operating mode is an elastic mode, where the chance that a tier instance is selected may vary depending on a statistical measure of an operating parameter in relation to lower and upper threshold values. Other embodiments, aspects and features are also disclosed.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: July 14, 2015
    Assignee: Nexenta Systems, Inc.
    Inventors: Alexander Aizman, Boris Protopopov
  • Working set swapping using a sequentially ordered swap file
    Patent number: 9081702
    Abstract: Techniques described enable efficient swapping of memory pages to and from a working set of pages for a process through the use of large writes and reads of pages to and from sequentially ordered locations in secondary storage. When writing pages from a working set of a process into secondary storage, the pages may be written into reserved, contiguous locations in a dedicated swap file according to a virtual address order or other order. Such writing into sequentially ordered locations enables reading in of clusters of pages in large, sequential blocks of memory, providing for more efficient read operations to return pages to physical memory.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: July 14, 2015
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mehmet Iyigun, Yevgeniy (Eugene) Bak, Landy Wang, Arun U. Kishan
  • Mechanisms to bound the presence of cache blocks with specific properties in caches
    Patent number: 9075730
    Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache and one or more sources for memory requests. In response to receiving a request to allocate data of a first type, a cache controller allocates the data in the cache responsive to determining a limit of an amount of data of the first type permitted in the cache is not reached. The controller maintains an amount and location information of the data of the first type stored in the cache. Additionally, the cache may be partitioned with each partition designated for storing data of a given type. Allocation of data of the first type is dependent at least upon the availability of a first partition and a limit of an amount of data of the first type in a second partition.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 7, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mithuna S. Thottethodi, Gabriel H. Loh, James M. O'Connor, Yasuko Eckert, Bradford M. Beckmann