Patents Examined by Hiep Nguyen
  • Patent number: 8868840
    Abstract: Provided is an information processing device including a holding portion of a cache link that is formed such that, when clusters are recorded on a predetermined recording medium by a FAT file system and a FAT formed by link information of the clusters is also recorded on the predetermined recording medium by the system, an entry is arranged for each of the clusters located at a predetermined interval, the entry being formed by information including the link information extracted from the FAT, an information update portion that, when updating the cache link after data is additionally written to the clusters on the recording medium, updates the information for an update target entry among entries forming the cache link, and a configuration conversion portion that removes the update target entry updated from an original position in the cache link, and connects it to an endmost position of the cache link.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: October 21, 2014
    Assignee: Sony Corporation
    Inventor: Takuma Mabuchi
  • Patent number: 8862815
    Abstract: A system and method for reading files stored on a storage system is disclosed. The method includes communicatively coupling one or more remote systems for reading files stored in storage with a first set of files according to a predetermined data format and in a cache memory with a second set of files, the second set of files being a subset of the first set of files. Next one or more remote systems are received at least one read request for reading a sequence of files. A determination is made, among the files of the sequence of files, whether one or more cached files are already stored in the cache memory and whether one or more remaining files are not already stored in the cache memory. Creating, within the one or more remaining files, an order according to which the remaining files should be read on the storage system.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Evangelos S. Eleftheriou, Robert Haas, Nils Haustein, Jens Jelitto, Ioannis Koltsidas, Slavisa Sarafijanovic, Alexander Saupp, Harald Seipp
  • Patent number: 8856449
    Abstract: A query cache stores queries and corresponding results of the queries, the results of the queries being derived from a primary store. A differential store stores a pointer to data of the primary store which has changed and which affects the result of the queries stored in the query store. A new query may be satisfied by accessing the corresponding query in the query store and determining, by reference to the differential store, whether data relating to the query in the primary store has changed since the query store was compiled and, completing the new query, by accessing the corresponding data in the primary store, if applicable. Data in the differential store may be arranged and partitioned according to labels. The partitioning may be varied according to predetermined rules.
    Type: Grant
    Filed: November 27, 2009
    Date of Patent: October 7, 2014
    Assignee: Nokia Corporation
    Inventors: Channabasappa Mudigowdra, Harsha Sathyanarayana Naga, Kavila Khatawate, Sukanta Banik, Venkata Subba Raju Ganapathi Raju, Pramod (Das Pramod) Pramod Das, Ashok Kumar
  • Patent number: 8856462
    Abstract: A system, method and computer program product for seismic imaging implements a seismic imaging algorithm utilizing Reverse Time Migration technique requiring large communication bandwidth and low latency to convert a parallel problem into one solved using massive domain partitioning. Since in RTM, both the forward and reverse wave propagation is iteratively calculated on time step increments, the method implements methods that includes partitioning memory between computation and intermediate results to optimize an RTM computation. The methods make maximum use of the memory to either eliminate storing the snapshot wavefield data to disk, or hide all or a significant portion of the disk I/O time. Furthermore, the schemes can provide the flexibility to vary a number of iterations (step size) for each snapshot to be kept in the memory. If any of the given conditions changes during the process, maximum usage of the available memory is ensured.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventor: Ligang Lu
  • Patent number: 8850114
    Abstract: The invention is an improved storage array controller that adds a level of indirection between host system and storage array. The storage array controller controls a storage array comprising at least one solid-state storage device. The storage array controller improvements include: garbage collection, sequentialization of writes, combining of writes, aggregation of writes, increased reliability, improved performance, and addition of resources and functions to a computer system with a storage subsystem.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: September 30, 2014
    Inventors: Daniel L Rosenband, Michael John Sebastian Smith
  • Patent number: 8843716
    Abstract: Speed of processing of transferring data stored in a storage apparatus to an external apparatus is increased. A storage apparatus according to the present invention: creates a non-decompression volume set to refer to a compression pool that compresses and stores data; decompresses and provides the data stored in the compression pool to a host computer; and provides the compressed data as is to other external apparatuses via the non-decompression volume.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: September 23, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Katsunori Suzuki, Hiroshi Nasu, Daisuke Shinohara
  • Patent number: 8838893
    Abstract: A method of providing data storage is disclosed that includes writing a plurality of data non-sequentially to at least one first storage drive, the at least one first storage drive having a random first input/output operations per second (IOPS) speed, and writing the plurality of data and an associated plurality of journal metadata sequentially to at least one second storage drive, the at least one second storage drive having a second random IOPS speed that is slower than the first random IOPS speed.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: September 16, 2014
    Assignee: Nexsan Corporation
    Inventors: Andrew Randall, Alastair Bryers, Thomas F. Gosnell
  • Patent number: 8832407
    Abstract: According to one embodiment, a communication device includes a data storage device and following units. The reception unit receives data and information indicating a size of the data. The data storage device includes a data area controlled by a file system and a temporary area beyond control of the file system. The determination unit determines whether the size is not larger than a predetermined threshold value. If it is determined that the size is not larger than the threshold value, the control unit writes the received data to the temporary area, copies the received data in the temporary area to the data area after completion of reception, and erases the received data in the temporary area after copying.
    Type: Grant
    Filed: August 1, 2012
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tomoya Horiguchi
  • Patent number: 8832411
    Abstract: Techniques described enable efficient swapping of memory pages to and from a working set of pages for a process through the use of large writes and reads of pages to and from sequentially ordered locations in secondary storage. When writing pages from a working set of a process into secondary storage, the pages may be written into reserved, contiguous locations in a dedicated swap file according to a virtual address order or other order. Such writing into sequentially ordered locations enables reading in of clusters of pages in large, sequential blocks of memory, providing for more efficient read operations to return pages to physical memory.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: September 9, 2014
    Assignee: Microsoft Corporation
    Inventors: Mehmet Iyigun, Yevgeniy Bak, Landy Wang, Arun U. Kishan
  • Patent number: 8832406
    Abstract: Systems and methods for data classification to facilitate and improve data management within an enterprise are described. The disclosed systems and methods evaluate and define data management operations based on data characteristics rather than data location, among other things. Also provided are methods for generating a data structure of metadata that describes system data and storage operations. This data structure may be consulted to determine changes in system data rather than scanning the data files themselves.
    Type: Grant
    Filed: December 11, 2013
    Date of Patent: September 9, 2014
    Assignee: CommVault Systems, Inc.
    Inventors: Anand Prahlad, Jeremy A. Schwartz, David Ngo, Brian Brockway, Marcus S. Muller
  • Patent number: 8832376
    Abstract: One embodiment of the present invention relates to a CPU cache system that stores tag information and cached data in the same SRAM. The system includes an SRAM memory device, a lookup buffer, and a cache controller. The SRAM memory device includes a cache data section and a cache tag section. The cache data section includes data entries and the tag section includes tag entries associated with the data entries. The tag entries include memory addresses that correspond to the data entries. The lookup buffer includes lookup entries associated with at least a portion of the data entries. The number of lookup entries is less than the number of tag entries. The cache controller is configured to perform a speculative read of the cache data section and a cache check of the lookup buffer simultaneously or in a single cycle.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: September 9, 2014
    Assignee: Infineon Technologies AG
    Inventor: Patrice Woodward
  • Patent number: 8832382
    Abstract: A method and apparatus for managing a virtual address to physical address translation utilize a subpage level fault detecting and access. The method and apparatus may also use an additional subpage and page store Non-Volatile Store (NVS). The method and apparatus determines whether a page fault occurs or whether a subpage fault occurs to effect an address translation and also operates such that if a subpage fault had occurred, a subpage is loaded corresponding to the fault from a NVS to a DRAM, such as DRAM or any other suitable volatile memory historically referred to as main memory. The method and apparatus, if a page fault has occurred, determines if a page fault has occurred without operating system assistance and is a hardware page fault detection system that loads a page corresponding to the fault from NVS to DRAM.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: September 9, 2014
    Assignee: ATI Technologies ULC
    Inventors: David E. Mayhew, Mark Hummel
  • Patent number: 8825959
    Abstract: A system and method for buffer management in a database are provided in which a predictive buffer manager may be used. The predictive buffer manager and process may predict when each block in a buffer is going to be used and then manages the buffer based on the prediction.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: September 2, 2014
    Assignee: Actian Netherlands B.V.
    Inventors: Michal Switakowski, Peter Boncz, Marcin Zukowski
  • Patent number: 8825968
    Abstract: An information processing apparatus includes a first storage unit and a processor. The first storage unit includes a first storage area. The processor receives a first request to write first data into the first storage area. The processor requests an external apparatus to write the first data into a second storage area in a second storage unit included in the external apparatus. The processor determines whether a first response has been received from the external apparatus. The first response indicates that the first data has been written into the second storage area. The processor writes the first data into the first storage area when the first response has been received. The processor requests, without writing the first data into the first storage area, the external apparatus to write second data stored in the first storage area into the second storage area when the first response has not been received.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: September 2, 2014
    Assignee: Fujitsu Limited
    Inventors: Masahisa Tamura, Yasuo Noguchi, Kazutaka Ogihara, Yoshihiro Tsuchiya, Takashi Watanabe, Tatsuo Kumano, Kazuichi Oe, Toshihiro Ozawa
  • Patent number: 8812777
    Abstract: A nonvolatile memory device includes: N (N is an integer equal to or greater than 2) number of nonvolatile memory cells disposed in a flag area of a page, N number of flag page buffers configured to input and output flag data to and from the nonvolatile memory cells of the flag area, and a data input/output control unit configured to select R number of flag page buffers so that the flag data is inputted and outputted from the R selected flag page buffers and no flag data is inputted and outputted through unselected N-R number of flag page buffers, wherein no one flag page buffer of the R selected flag page buffers is immediately adjacent to another one of the R selected flag page buffers.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: August 19, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae-Won Cha, Sung-Hoon Ahn
  • Patent number: 8812780
    Abstract: A RAID group control device for performing access control over one or more RAID groups each having redundancy. The RAID group control device includes an acquiring unit to acquire access frequency information with respect to a RAID group among the one or more RAID groups; a scheduling unit to find a time period exhibiting a lower access frequency than access frequencies of anterior and posterior time periods in a specified time range on the basis of the access frequency information, and to determine start timing of a process of rewriting firmware of drives belonging to the RAID group on the basis of the found time period; and a firmware rewrite processing unit to start the process of rewriting the firmware of the drives at the determined start timing.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Limited
    Inventors: Masahiro Yoshida, Tadashi Matsumura
  • Patent number: 8799579
    Abstract: A multi-core processor providing heterogeneous processor cores and a shared cache is presented.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: August 5, 2014
    Assignee: Intel Corporation
    Inventors: Frank T. Hady, Mason B. Cabot, John Beck, Mark B. Rosenbluth
  • Patent number: 8799577
    Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: August 5, 2014
    Assignee: Intel Corporation
    Inventors: Christopher J. Hughes, Yen-Kuang Chen, Changkyu Kim, Daehyun Kim, Victor W. Lee, Anthony-Trung D. Nguyen, Nadathur Rajagopalan Satish
  • Patent number: 8793454
    Abstract: An extended command is defined in compliance with the ATA standard. A selection number for selecting one of HDDs, one or more designated ATA commands, and an accessible time period including an available count are added to the extended command. As a result, designated normal ATA commands can access a certain one of the HDDs for a certain time period.
    Type: Grant
    Filed: June 5, 2012
    Date of Patent: July 29, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Akihiro Matsumoto
  • Patent number: 8788776
    Abstract: A hard disk control method, a hard disk control device and a computer are provided The method includes detecting the current mode in which the system runs; determining the access frequency of the hard disk in the system when detecting the system runs in an idle mode currently; intercepting the hard disk access commands to be sent to the hard disk when the access frequency of the hard disk is lower than a predetermined access frequency threshold to make the hard disk enter into a preset power saving mode, and saving the hard disk access commands into a preset memory.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: July 22, 2014
    Assignees: Beijing Lenovo Software Ltd, Lenovo (Beijing) Co., Ltd.
    Inventor: Xianqun Yi