Patents Examined by Hoa B. Trinh
  • Patent number: 10752805
    Abstract: Provided is a composition for forming a film for semiconductor devices, including: a compound (A) including a Si—O bond and a cationic functional group containing at least one of a primary nitrogen atom or a secondary nitrogen atom; a crosslinking agent (B) which includes three or more —C(?O)OX groups (X is a hydrogen atom or an alkyl group having from 1 to 6 carbon atoms) in the molecule, in which from one to six of three or more —C(?O)OX groups are —C(?O)OH groups, and which has a weight average molecular weight of from 200 to 600; and a polar solvent (D).
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: August 25, 2020
    Assignee: MITSUI CHEMICALS, INC.
    Inventors: Yasuhisa Kayaba, Hirofumi Tanaka, Koji Inoue
  • Patent number: 10756058
    Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first chip, a second chip, self-aligned structures, a bridge structure, and an insulating encapsulant. The first chip has a first rear surface opposite to a first active surface. The second chip is disposed beside the first chip and has a second rear surface opposite to a second active surface. The self-aligned structures are disposed on the first rear surface of the first chip and the second rear surface of the second chip. The bridge structure is electrically connected to the first chip and the second chip. The insulating encapsulant covers at least the side surfaces of the first and second chips, a side surface of the semiconductor substrate, and the side surfaces of the self-aligned structures.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: August 25, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Ching Shih, Chih-Wei Wu, Szu-Wei Lu
  • Patent number: 10756090
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 25, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Patent number: 10748850
    Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 18, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng Lin, Takashi Noma, Francis J. Carney
  • Patent number: 10741402
    Abstract: An electronic device, an electronic module comprising the electronic device and methods for fabricating the same are disclosed. In one example, the electronic device includes a semiconductor substrate and a metal stack disposed on the semiconductor substrate, wherein the metal stack comprises a first layer, wherein the first layer comprises NiSi.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 11, 2020
    Assignee: Infineon Technologies AG
    Inventors: Paul Frank, Gretchen Adema, Thomas Bertaud, Michael Ehmann, Eric Graetz, Kamil Karlovsky, Evelyn Napetschnig, Werner Robl, Tobias Schmidt, Joachim Seifert, Frank Wagner, Stefan Woehlert
  • Patent number: 10734969
    Abstract: A vibrator device includes a circuit element, which has a first terminal and is a quadrangle in plan view, a vibrator, which is disposed on an active surface and is a quadrangle in plan view, a base, on which the circuit element is disposed and which has a second terminal, and a wire which connects the first terminal and the second terminal together. In plan view of the circuit element, at least one side of the vibrator is disposed along a direction where the one side intersects each of two adjacent sides of the circuit element, and the vibrator does not overlap the first terminal.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: August 4, 2020
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Hisahiro Ito
  • Patent number: 10734321
    Abstract: An integrated circuit includes a set of active regions in a substrate, a first set of conductive structures, a shallow trench isolation (STI) region, a set of gates and a first set of vias. The set of active regions extend in a first direction and is located on a first level. The first set of conductive structures and the STI region extend in at least the first direction or a second direction, is located on the first level, and is between the set of active regions. The STI region is between the set of active regions and the first set of conductive structures. The set of gates extend in the second direction and overlap the first set of conductive structures. The first set of vias couple the first set of conductive structures to the set of gates.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pochun Wang, Ting-Wei Chiang, Chih-Ming Lai, Hui-Zhong Zhuang, Jung-Chan Yang, Ru-Gun Liu, Ya-Chi Chou, Yi-Hsiung Lin, Yu-Xuan Huang, Yu-Jung Chang, Guo-Huei Wu, Shih-Ming Chang
  • Patent number: 10730745
    Abstract: A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: August 4, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Il Kwon Shim
  • Patent number: 10727214
    Abstract: A method for manufacturing an integrated circuit (IC) device. A first IC wafer is diced to obtain a first superdie including a plurality of first die. A second IC wafer is diced to obtain a second superdie including a plurality of second die. The first superdie and the second superdie are placed on an interposer substrate to form at least part of a composite IC wafer, wherein each of the first die is aligned with a respective one of the second die in the composite IC wafer. The composite IC wafer is diced to obtain a plurality of IC devices, where each of the IC devices includes a respective one of the first die and the second die with which it is aligned.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: July 28, 2020
    Assignee: Synaptics Incorporated
    Inventor: Stephen L. Morein
  • Patent number: 10727153
    Abstract: A semiconductor device and a method of manufacturing the same include a die and a planar thermal layer, and a thick-silver layer having a thickness of at least four (4) micrometers disposed directly onto a first planar side of the planar thermal layer, as well as a metallurgical die-attach disposed between the thick-silver layer and the die, the metallurgical die-attach directly contacting the thick-silver layer.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: July 28, 2020
    Assignee: NXP USA, Inc.
    Inventors: Lakshminarayan Viswanathan, Jaynal A Molla
  • Patent number: 10727133
    Abstract: A method of forming a gate structure with an undercut region includes, among other things, forming a plurality of fins above a substrate and an isolation structure above the substrate and between the plurality of fins, forming a placeholder gate structure above the plurality of fins in a first region and above the isolation structure in a second region, selectively removing a portion of the placeholder structure in the second region to define an undercut recess, forming a spacer structure adjacent the sacrificial gate structure, forming a dielectric layer adjacent the spacer structure and in the undercut recess, removing remaining portions of the placeholder gate structure to define a gate cavity, and forming a replacement gate structure in the gate cavity.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Qun Gao, Balaji Kannan, Shesh Mani Pandey, Haiting Wang
  • Patent number: 10714411
    Abstract: An IC chip structure including a plurality of IC chips electrically connected to one another in back-end-of-line (BEOL) interconnect layer of the structure is disclosed. The IC structure may include openings in crack-stop structures surrounding the IC chips and a interconnect wire extending between the IC chips through the openings. A packaging structure for utilizing the IC structure where at least one IC chip is inoperable is also disclosed. The structure may include a first bond pad array on a top surface of a packaging substrate including operable bond pads connected to an operable IC chip and structural support bond pads connected to the inoperable IC chip; a second bond pad array on a bottom surface of the substrate including operable bond pads connected to a single IC chip printed circuit board; and an interconnect structure for connecting the operable bond pads of the first and second bond pad arrays.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: July 14, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Wolfgang Sauter, Mark W. Kuemerle, Eric W. Tremble, David B. Stone, Nicholas A. Polomoff, Eric S. Parent, Jawahar P. Nayak, Seungman Choi
  • Patent number: 10700021
    Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Andrew J. Brown, Rahul Jain, Prithwish Chatterjee, Lauren A. Link, Sai Vadlamani
  • Patent number: 10693039
    Abstract: A light-emitting device comprises a light-emitting stack; a reflective structure comprising a reflective layer on the light-emitting stack and a first insulating layer covering the reflective layer; and a first conductive layer on the reflective structure; wherein the first insulating layer isolates the reflective layer from the first conductive layer.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: June 23, 2020
    Assignee: Epistar Corporation
    Inventors: Wen-Luh Liao, Shao-Ping Lu, Hung-Ta Cheng, Shih-I Chen, Chia-Liang Hsu, Shou-Chin Wei, Ching-Pei Lin, Yu-Ren Peng, Chien-Fu Huang, Wei-Yu Chen, Chun-Hsien Chang
  • Patent number: 10685947
    Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Mark T. Bohr, Rajesh Kumar, Robert L. Sankman, Ravindranath V. Mahajan, Wesley D. Mc Cullough
  • Patent number: 10672774
    Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following steps. A polysilicon layer is formed on a substrate. A sacrificial layer is formed on the polysilicon layer. An implantation process is performed on the sacrificial layer and the polysilicon layer. The sacrificial layer is removed. A metal stack is formed on the polysilicon layer. The present invention also provides another method of forming a bit line gate structure of a dynamic random access memory (DRAM) including the following steps. A polysilicon layer is formed on a substrate. A plasma doping process is performed on a surface of the polysilicon layer. A metal stack is formed on the surface of the polysilicon layer.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: June 2, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wei Chen, Pin-Hong Chen, Tsun-Min Cheng, Chun-Chieh Chiu
  • Patent number: 10672664
    Abstract: In an embodiment, a method includes forming at least one trench in non-device regions of a first surface of a semiconductor wafer, the non-device regions being arranged between component positions, the component positions including device regions and a first metallization structure, applying a first polymer layer to the first surface of a semiconductor wafer such that the trenches and edge regions of the component positions are covered with the first polymer layer and such that at least a portion of the first metallization structure is uncovered by the first polymer layer, removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, revealing portions of the first polymer layer in the non-device regions and producing a worked second surface and inserting a separation line through the first polymer layer in the non-device regions to form a plurality of separate semiconductor dies.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: June 2, 2020
    Assignee: Infineon Technologies AG
    Inventors: Paul Ganitzer, Carsten von Koblinski, Thomas Feil, Gerald Lackner, Jochen Mueller, Martin Poelzl, Tobias Polster
  • Patent number: 10658296
    Abstract: A method for semiconductor manufacturing is disclosed. The method includes receiving a device having a first surface through which a first metal or an oxide of the first metal is exposed. The method further includes depositing a dielectric film having Si, N, C, and O over the first surface such that the dielectric film has a higher concentration of N and C in a first portion of the dielectric film near the first surface than in a second portion of the dielectric film further away from the first surface than the first portion. The method further includes forming a conductive feature over the dielectric film. The dielectric film electrically insulates the conductive feature from the first metal or the oxide of the first metal.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Wu, Li-Hsuan Chu, Ching-Wen Wen, Chia-Chun Hung, Chen Liang Chang, Chin-Szu Lee, Hsiang Liu
  • Patent number: 10651052
    Abstract: A semiconductor package structure includes a first insulating layer, a first conductive layer, a multi-layered circuit structure, a protection layer, and a semiconductor chip electrically connected to the multi-layered circuit structure. The first insulating layer defines a first through hole extending through the first insulating layer. The first conductive layer includes a conductive pad disposed in the first through hole and a trace disposed on an upper surface of the first insulating layer. The multi-layered circuit structure is disposed on an upper surface of the first conductive layer. The multi-layered circuit structure includes a bonding region disposed on the conductive pad of the first conductive layer and an extending region disposed on the trace of the first conductive layer. The protection layer covers the upper surface of the first insulating layer and the extending region of the multi-layered circuit structure, and exposes the bonding region of the multi-layered circuit structure.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 12, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yan Wen Chung
  • Patent number: 10651293
    Abstract: A vertical transistor device includes a vertically oriented channel semiconductor structure, a bottom source/drain (S/D) region, a top source/drain (S/D) region, and a gate structure positioned around the vertically oriented channel semiconductor structure, above the bottom source/drain (S/D) region, and below the top source/drain (S/D) region. The gate structure includes a gate electrode and a gate insulation layer positioned between the gate electrode and at least a portion of the vertically oriented channel semiconductor structure. A top spacer is positioned between the gate electrode and at least a portion of the top source/drain (S/D) region, a bottom spacer is positioned between the gate electrode and at least a portion of the bottom source/drain (S/D) region, and a gate cap is positioned around an outer perimeter surface of the gate structure, wherein the top spacer, the bottom spacer, and the gate cap all include a same insulating material.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: John H. Zhang