Abstract: An electroluminescent display device and a light emitting device including a blue light emitting layer include a first electrode, a second electrode, and a light emitting layer between the first electrode and the second electrode. The light emitting layer includes a blue light emitting layer including a plurality of nanostructures, the plurality of nanostructures does not include cadmium. On an application of a bias voltage, the blue light emitting layer is configured to emit light of an emission peak wavelength (?max) in a range of greater than or equal to about 445 nm and less than or equal to about 480 nm.

Abstract: A semiconductor package including a semiconductor chip, a redistribution layer structure disposed under the semiconductor chip, a bump pad disposed under the redistribution layer structure and having an upper structure of a first width and a lower structure of a second width less than the first width, a metal seed layer disposed along a lower surface of the upper structure and a side surface of the lower structure, an insulating layer surrounding the redistribution layer structure and the bump pad, and a bump structure disposed under the bump pad. A first undercut is disposed at one end of the metal seed layer that contacts the upper structure, and a second undercut is disposed at an other end of the metal seed layer that contacts the lower.

Abstract: A method of direct hybrid bonding first and second semiconductor elements of differential thickness is disclosed. The method can include patterning a plurality of first contact features on the first semiconductor element. The method can include second a plurality of second contact features on the second semiconductor element corresponding to the first contact features for direct hybrid bonding. The method can include applying a lithographic magnification correction factor to one of the first patterning and second patterning without applying the lithographic magnification correction factor to the other of the first patterning and the second patterning. In various embodiments, a differential expansion compensation structure can be disposed on at least one of the first and the second semiconductor elements.

Abstract: An integrated circuit includes a first and second active region, a first conductive structure, an insulating region, a set of gates and a set of contacts. The first and second active region are in a substrate, extend in a first direction, are located on a first level, and being separated from one another in a second direction. The first conductive structure extends in the first direction, is located on the first level, and is between the first and second active region. The insulating region is located on at least the first level, and is between the first and second active region and the first conductive structure. The set of gates extend in the second direction, overlap the first conductive structure, and is located on a second level. The set of contacts extend in the second direction, overlap the first conductive structure, and is located on the second level.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a die-level interposer having a first surface and an opposing second surface; a first die coupled to the first surface of the die-level interposer by a first hybrid bonding region having a first pitch; a second die coupled to the second surface of the die-level interposer by a second hybrid bonding region having a second pitch different from the first pitch; and a third die coupled to the second surface of the die-level interposer by a third hybrid bonding region having a third pitch different from the first and second pitches.

Abstract: Provided is a semiconductor module, including: a semiconductor chip including a semiconductor substrate and a metal electrode provided above the semiconductor substrate; a protective film provided above the metal electrode; a plated layer provided above the metal electrode, having at least a part being in a height identical to the protective film; a solder layer provided above the plated layer; and a lead frame provided above the solder layer, wherein the plated layer is provided in a range not in contact with the protective film.

Abstract: A semiconductor device comprises a substrate body with a surface, a conductor comprising a conductor material covering at least part of the surface, and a dielectric that is arranged on a part of the surface that is not covered by the conductor. Therein, the conductor is in contact with the substrate body, the conductor and the dielectric form a layer, and a bonding surface of the layer has surface topographies of less than 10 nm, with the bonding surface facing away from the substrate body. Moreover, the semiconductor device is free of a diffusion barrier.

Abstract: Disclosed herein is a heat spreader for use with an IC package, the heat spreader having features for enhanced temperature control of the IC package. A heat spreader for use with an IC package is disclosed. In one example, the heat spreader includes a metal body that has a sealed internal cavity. A thermally conductive material fills the sealed internal cavity. The thermally conductive material has an interstitial space sufficient to allow fluid to pass therethrough. A first phase change material fills at least a portion of the interstitial space of the thermally conductive material.

Abstract: In an embodiment, a device includes: a dielectric layer over an active surface of a semiconductor substrate; a conductive via in the dielectric layer, the conductive via including a first copper layer having a non-uniform grain orientation; and a bonding pad over the conductive via and in the dielectric layer, the bonding pad including a second copper layer having a uniform grain orientation, a top surface of the bonding pad being coplanar with a top surface of the dielectric layer.

Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

Abstract: In a described example, an apparatus includes: a first mold compound partially covering a thermal pad that extends through a pre-molded package substrate formed of a first mold compound, a portion of the thermal pad exposed on a die side surface of the pre-molded package substrate, the pre-molded package substrate having a recess on the die side surface, with an exposed portion of the thermal pad and a portion of the first mold compound in a die mounting area in the recess; a semiconductor die mounted to the thermal pad and another semiconductor die mounted to the mold compound in the die mounting area; wire bonds coupling bond pads on the semiconductor dies to traces on the pre-molded package substrate; and a second mold compound over the die side surface of the pre-molded package substrate and covering the wire bonds, the semiconductor dies, the recess, and a portion of the traces.

Abstract: A semiconductor device includes a chip body; a passivation layer on the chip body; a lower dielectric layer on the passivation layer; a first re-distribution pad on the lower dielectric layer; an upper dielectric layer on the lower dielectric layer, the upper dielectric layer having a groove that exposes an upper surface of the first re-distribution pad; and a second re-distribution pad on the upper dielectric layer. An upper surface of the second re-distribution pad is positioned at a higher level than the upper surface of the first re-distribution pad.

Abstract: A semiconductor device includes a semiconductor element, a conductive member, and solder portions. The semiconductor element includes first main electrodes and a protective film on a first main surface, and a second main electrode on a second main surface. The protective film has an interposed film portion between the first main electrodes. The conductive member has facing portions each facing a corresponding one of the first main electrodes and an interposed conductive portion disposed between the facing portions. The solder portions are disposed between the first main electrodes and the facing portions and separated away from each other by the interposed film portion and the interposed conductive portion to define a space between the solder portions. The interposed film portion and the interposed conductive portion are less likely wetted to the solder portions to avoid the solder portions in liquid phase entering into the space during soldering.

Abstract: A method for manufacturing a light-emitting element includes forming a first light-emitting part, forming a tunnel junction part on the first light-emitting part, and forming a second light-emitting part on the tunnel junction part. The step of forming the first light-emitting part includes forming a first layer with a first p-type impurity concentration at a first temperature, and forming a second layer with a second p-type impurity concentration on the first layer. The second p-type impurity concentration is greater than the first p-type impurity concentration. The step of forming the second light-emitting part includes forming a third layer with a third p-type impurity concentration at a second temperature and forming a fourth layer with a fourth p-type impurity concentration on the third layer. The fourth p-type impurity concentration is greater than the third p-type impurity concentration. The second temperature is less than the first temperature.

Abstract: An integrated circuit structure includes an aluminum pad layer on a dielectric stack, a passivation layer covering the aluminum pad layer, and an aluminum shield layer including aluminum routing patterns disposed directly above an embedded memory area and embedded in the dielectric stack. The aluminum shield layer is electrically connected to the uppermost copper layer through a plurality of tungsten vias. The plurality of tungsten vias is embedded in the dielectric stack.

Abstract: A semiconductor device includes a first redistribution layer pattern, a second redistribution layer pattern, and a recognition mark. The first redistribution layer pattern is formed on a semiconductor substrate. The second redistribution layer pattern, with a bonding pad portion, is disposed on the first redistribution layer pattern. Furthermore, the recognition mark is formed on the first redistribution layer pattern to indicate a position of the bonding pad portion.

Abstract: An electronic device that includes a base member made of a material containing metal atoms, the base member having a bonding surface, and the bonding surface contains oxides of the metal atoms; an electronic element is mounted on the base member; an organic structure on the bonding surface of the base member; and a cover member bonded to the bonding surface of the base member via the organic structure so as to encapsulate the electronic element in a space between the base member and the cover member.

Abstract: A display panel, a method of manufacturing the display panel, and a display device are provided. According to the display panel provided by the embodiment of the present application, a bonding structure is arranged between a display substrate and a circuit board to connect the display substrate and the circuit board together, and a width of the bonding structure is set to be 50 microns (?m)-200 ?m, so that when a plurality of display panels are spliced to realize a large-screen display, a width of an interval area between the adjacent display areas of the display panels may be significantly reduced.

Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure and a first connecting structure, wherein the first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. A porosity of the first porous layer is between about 25% and about 100%. The first semiconductor structure includes a plurality of first composite conductive features, wherein at least one of the plurality of first composite conductive features includes a first protection liner, a first graphene liner in the first protection liner and a first core conductor in the first graphene liner.

Abstract: In an embodiment, a semiconductor device includes a semiconductor body having a first major surface, a second major surface opposing the first major surface and at least one transistor device structure, a source pad and a gate pad arranged on the first major surface, a drain pad and at least one further contact pad coupled to a further device structure. The drain pad and the at least one further contact pad are arranged on the second major surface.