Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

Abstract: A method of manufacturing a semiconductor package substrate includes forming a trench and a post by etching an upper surface of a base substrate including a conductive material, filling the trench with a resin, removing the resin exposed to outside of the trench such that an upper surface of the post and an upper surface of the resin are at same level, forming a conductive layer on an entire area of the upper surface of the post and the upper surface of the resin, and forming a circuit wiring including an upper circuit wiring and a lower circuit wiring by simultaneously patterning the conductive layer and a lower surface of the base substrate.

Abstract: A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.

Abstract: An electronic component includes a semiconductor device including a semiconductor die including a first surface, the first surface including a first metallization structure and edge regions surrounding the first metallization structure, a second surface opposing the first surface and including a second metallization structure, and side faces extending between the first surface and the second surface, wherein the edge regions of the first surface and portions of the side faces are covered by a first polymer layer, wherein the electronic component further includes a plurality of leads and a plastic housing composition, wherein the first metallization structure is coupled to a first lead and the second metallization structure is coupled to a second lead of the plurality of leads.

Abstract: A semiconductor package includes a base substrate and an interposer substrate. The interposer substrate includes a semiconductor substrate, a first passivation layer, a wiring region, a through via penetrating through the semiconductor substrate and the first passivation layer, and a second passivation layer covering at least a portion of the first passivation layer and having an opening exposing a lower surface of the through via. The semiconductor package further includes a conductive pillar extending from the opening of the second passivation layer; and a conductive bump disposed between the conductive pillar and the base substrate. The opening of the second passivation layer has inclined side surfaces such that a width of the opening decreases towards the first passivation layer, and side surfaces of the conductive pillar are positioned to overlap the inclined side surfaces of the second passivation layer in a vertical direction.

Abstract: A method of attaching a metal clip to a semiconductor die includes: aligning a first bonding region of the metal clip with a first bond pad of the semiconductor die; and while the first bonding region of the metal clip is aligned with the first bond pad of the semiconductor die, forming a plurality of first wire bonds to the first bond pad of the semiconductor die through a plurality of openings in the first bonding region of the metal clip, the plurality of first wire bonds forming a joint between the metal clip and the first bond pad of the semiconductor die. Additional methods and related semiconductor packages produced from such methods are also described.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises an interposer, a first die attached to the interposer, and a second die attached to the interposer. In an embodiment, the electronic package further comprises a heatsink thermally coupled to the first die and the second die. In an embodiment, the heatsink has a first surface facing away from the first die and the second die and a second surface facing the first die and the second die. In an embodiment, the heatsink comprises a thermal break between the first die and the second die.

Abstract: The present application provides a semiconductor package with air gaps for reducing capacitive coupling between conductive features and a method for manufacturing the semiconductor package. The semiconductor package includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure has a first bonding surface. The second semiconductor structure has a second bonding surface partially in contact with the first bonding surface. A portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package.

Abstract: A method includes forming a first passivation layer, forming a metal pad over the first passivation layer, forming a planarization layer having a planar top surface over the metal pad, and patterning the planarization layer to form a first opening. A top surface of the metal pad is revealed through the first opening. The method further includes forming a polymer layer extending into the first opening, and patterning the polymer layer to form a second opening. The top surface of the metal pad is revealed through the second opening.

Abstract: An optical semiconductor element mounting package as well as an optical semiconductor device using the package are provided. The optical semiconductor element mounting package has a recessed part that serves as an optical semiconductor element mounting region. The package includes a resin molding and at least a pair of positive and negative lead electrodes. The resin molding is composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part. The lead electrodes are disposed opposite to each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes.

Abstract: A semiconductor device includes a semiconductor element, which has a protective film having an opening that exposes a part of a source electrode and disposed/provided to position an end portion thereof on the source electrode. A rewiring layer has wiring that is connected to the source electrode and to a conductive connecting member, and an insulator that covers a part of the source wiring. The insulator includes: an insulating film having (a) an opening for exposing a part of the source wiring, and (b) an end portion of the opening provided in a facing region of the opening; and an insulating film having (c) (i) an opening for exposing a part of the source wiring having a solder arranged therein and (ii) a connecting member arranged therein.

Abstract: Techniques and mechanisms for coupling chiplets to microchips utilizing active bridges. The active bridges include circuits that provide various functions and capabilities that previously may have been located on the microchips and/or the chiplets. Furthermore, the active bridges may be coupled to the microchips and the chiplets via “native interconnects” utilizing direct bonding techniques. Utilizing the active bridges and the direct bonding techniques of the active bridges to the microchips and the chiplets, the pitch for the interconnects can be greatly reduced going from a pitch in the millimeters to a fine pitch that may be in a range of less than one micron to approximately five microns.

Abstract: A semiconductor device includes: a substrate including a semiconductor chip region, a guard ring region adjacent to the semiconductor chip region, and an edge region adjacent to the guard ring region; a first interlayer insulating layer disposed on the substrate; a wiring structure disposed inside the first interlayer insulating layer and in the guard ring region, wherein the wiring structure includes a first wiring layer and a second wiring layer disposed above the first wiring layer; and a trench configured to expose at least a part of the first interlayer insulating, layer in the edge region, wherein the trench includes a first bottom surface and a second bottom surface formed at a level different from that of the first bottom surface, wherein the first bottom surface is formed between the wiring structure and the second bottom surface, and the second bottom surface is formed adjacent to the first bottom surface.

Abstract: Techniques are described for the use of moats for isolating and singulating semiconductor devices formed on a wafer. Described techniques use dielectric films, such as an oxide-nitride film, to coat moat surfaces and provide passivation. The dielectric films may form a junction with a metal contact layer, to reduce electrical overstress that may otherwise occur in the resulting semiconductor devices. To ensure coverage of the moat surfaces, spray coating of a positive photoresist may be used.

Abstract: A method of forming a semiconductor device includes providing a carrier comprising a die attach pad, providing a semiconductor die that includes a bond pad disposed on a main surface of the semiconductor die, and providing a metal interconnect element, arranging the semiconductor die on the die attach pad such that the bond pad faces away from the die attach pad, and welding the metal interconnect element to the bond pad, wherein the bond pad comprises first and second metal layers, wherein the second metal layer is disposed between the first metal layer and a semiconductor body of the semiconductor die, wherein a thickness of the first metal layer is greater than a thickness of the second metal layer, and wherein the first metal layer has a different metal composition as the second metal layer.

Abstract: An electronic module for a half-bridge circuit includes a base substrate with an insulating layer between a first metal layer and a second metal layer. A trench formed through the first metal layer electrically isolates first, second, and third portions of the first metal layer from one another. A high-side switch includes an enhancement-mode transistor and a depletion-mode transistor. The depletion-mode transistor includes a III-N material structure on an electrically conductive substrate. A drain electrode of the depletion-mode transistor is connected to the first portion, a source electrode of the enhancement-mode transistor is connected to the second portion, a drain electrode of the enhancement-mode transistor is connected to a source electrode of the depletion-mode transistor, a gate electrode of the depletion-mode transistor is connected to the electrically conductive substrate, and the electrically conductive substrate is connected to the second portion.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip, first and second conductive members, a first connection member, and a resin portion. The first conductive member includes first and second portions. The second portion is electrically connected to the semiconductor chip. A direction from the semiconductor chip toward the second portion is aligned with a first direction. A direction from the second portion toward the first portion is aligned with a second direction crossing the first direction. The second conductive member includes a third portion. The first connection member is provided between the first and third portion. The first connection member is conductive. The resin portion includes a first partial region. The first partial region is provided around the first and third portions, and the first connection member. The first portion has a first surface opposing the first connection member and including a recess and a protrusion.

Abstract: A device includes a first side interconnect structure over a first side of a substrate, wherein active circuits are in the substrate and adjacent to the first side of the substrate, a dielectric layer over a second side of the substrate, a pad embedded in the dielectric layer, the pad comprising an upper portion and a bottom portion formed of two different materials and a passivation layer over the dielectric layer.

Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.