Patents Examined by Hoa B. Trinh
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Patent number: 12249572Abstract: An integrated structure intended to connect a plurality of semiconductor devices, the integrated structure including a substrate, a first face and a second face, the first face being intended to receive the semiconductor devices, the integrated structure including, at the first face, at least one routing level, the routing level or levels including: at least one first conductor routing track in a conductor material; and at least one first superconductor routing track made from a superconductor material.Type: GrantFiled: September 20, 2021Date of Patent: March 11, 2025Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVESInventors: Candice Thomas, Jean Charbonnier, Perceval Coudrain, Maud Vinet
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Patent number: 12237337Abstract: A first high voltage semiconductor element, disposed in a substrate, includes first trenches; a first source region and a first drain region; first drift regions having respective ones partially surround the first source region and the first drain region; a first gate insulating layer and a first gate electrode disposed between the first drift regions; and a first high voltage well surrounding the first drift regions. A second high voltage semiconductor element, disposed in the substrate, includes second trenches; a second source region and a second drain region; second drift regions having respective ones partially surround the second source region and the second drain region; a second gate insulating layer and a second gate electrode disposed between the second drift regions; and a second high voltage well surrounding the second drift regions. Depths of the second trenches are disposed to be greater than depths of the first trenches.Type: GrantFiled: October 27, 2021Date of Patent: February 25, 2025Assignee: SK keyfoundry Inc.Inventors: Boseok Oh, Kwangho Park, Jiman Kim, Taekyun Yoo
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Patent number: 12230605Abstract: A semiconductor package includes semiconductor bridge, first and second multilayered structures, first encapsulant, and a pair of semiconductor dies. Semiconductor dies of the pair include semiconductor substrate and conductive pads disposed at front surface of semiconductor substrate. Semiconductor bridge electrically interconnects the pair of semiconductor dies. First multilayered structure is disposed on rear surface of one semiconductor die. Second multilayered structure is disposed on rear surface of the other semiconductor die. First encapsulant laterally wraps first multilayered structure, second multilayered structure and the pair of semiconductor dies. Each one of first multilayered structure and second multilayered structure includes a top metal layer, a bottom metal layer, and an intermetallic layer. Each one of first multilayered structure and second multilayered structure has surface coplanar with surface of first encapsulant.Type: GrantFiled: February 7, 2023Date of Patent: February 18, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Ching Shih, Chih-Wei Wu, Szu-Wei Lu
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Wafer level package with polymer layer delamination prevention design and method of forming the same
Patent number: 12230593Abstract: A package structure is provided, including a substrate, a first passivation layer, a metallization layer, a second passivation layer, and a polymer layer. The first passivation layer is formed over the substrate. The metallization layer is conformally formed on the first passivation layer. The second passivation layer is conformally formed on the first passivation layer and the metallization layer. A step structure is formed on the top surface of the second passivation layer, and includes at least one lower part that is lower than the other parts of the step structure. The polymer layer is formed over the second passivation layer. A portion of the polymer layer extends into the lower part of the step structure to engage with the step structure.Type: GrantFiled: July 30, 2021Date of Patent: February 18, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kai-Heng Chen, Pei-Haw Tsao, Shyue-Ter Leu, Rung-De Wang, Chien-Chun Wang -
Patent number: 12218087Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure and a first connecting structure, wherein the first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. A porosity of the first porous layer is between about 25% and about 100%. The first semiconductor structure includes a plurality of first composite conductive features, wherein at least one of the plurality of first composite conductive features includes a first protection liner, a first graphene liner in the first protection liner and a first core conductor in the first graphene liner.Type: GrantFiled: March 7, 2024Date of Patent: February 4, 2025Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Teng-Yen Huang
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Patent number: 12218022Abstract: A method includes forming a first passivation layer, forming a metal pad over the first passivation layer, forming a planarization layer having a planar top surface over the metal pad, and patterning the planarization layer to form a first opening. A top surface of the metal pad is revealed through the first opening. The method further includes forming a polymer layer extending into the first opening, and patterning the polymer layer to form a second opening. The top surface of the metal pad is revealed through the second opening.Type: GrantFiled: July 20, 2023Date of Patent: February 4, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Hsiu Chen, Wen-Chih Chiou, Chen-Hua Yu
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Patent number: 12211805Abstract: A semiconductor device includes a first wafer comprising a first portion of a seal ring structure within a body of the first wafer. The semiconductor device includes a second wafer comprising a second portion of the seal ring structure within a body of the second wafer. The second wafer is affixed to the first wafer such that the second portion of the seal ring structure is on the first portion of the seal ring structure. The semiconductor device includes a trench structure comprising a first trench in the first wafer and a second trench in the second wafer, where the first trench and the second trench are on a same side of the seal ring structure.Type: GrantFiled: September 17, 2021Date of Patent: January 28, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Liang Lu, Chun-Wei Chia, Chun-Hao Chou, Kuo-Cheng Lee
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Patent number: 12206004Abstract: A method includes forming a p-well and an n-well in a substrate. The method further includes forming a stack of interleaving first semiconductor layers and second semiconductor layers over the p-well and the n-well, the first semiconductor layers having a first thickness and the second semiconductor layers having a second thickness different than the first thickness. The method further includes annealing the stack of interleaving semiconductor layers. The method further includes patterning the stack to form fin-shaped structures including a first fin-shaped structure over the n-well and a second fin-shaped structure over the p-well. The method further includes etching to remove the second semiconductor layers from the first and second fin-shaped structures, where the first semiconductor layers have a different thickness within each of the first and second fin-shaped structures after the etching. The method further includes forming a metal gate over the first and second fin-shaped structures.Type: GrantFiled: May 6, 2022Date of Patent: January 21, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Ju Chou, Yen-Po Lin, Jiun-Ming Kuo, Yuan-Ching Peng
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Patent number: 12205910Abstract: An integrated circuit device may include a multi-material toothed bond pad including (a) an array of vertically-extending teeth formed from a first material, e.g., aluminum, and (b) a fill material, e.g., silver, at least partially filling voids between the array of teeth. The teeth may be formed by depositing and etching aluminum or other suitable material, and the fill material may be deposited over the array of teeth and extending down into the voids between the teeth, and etched to expose top surfaces of the teeth. The array of teeth may collectively define an abrasive structure. The multi-material toothed bond pad may be bonded to another bond pad, e.g., using an ultrasonic or thermosonic bonding process, during which the abrasive teeth may abrade, break, or remove unwanted native oxide layers formed on the respective bond pad surfaces, to thereby create a direct and/or eutectic bonding between the bond pads.Type: GrantFiled: May 1, 2023Date of Patent: January 21, 2025Assignee: Microchip Technology IncorporatedInventors: Justin Sato, Bomy Chen, Yaojian Leng, Gerald Marsico, Julius Kovats
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Patent number: 12205874Abstract: A semiconductor package includes: a semiconductor die attached to a leadframe and having a first bond pad at a side of the semiconductor die facing away from the leadframe; a metal clip having a first bonding region attached to the first bond pad of the semiconductor die by a plurality of first wire bonds which extend through a plurality of first openings in the first bonding region of the metal clip, the plurality of first wire bonds forming a joint between the metal clip and the first bond pad of the semiconductor die; and a joint between the plurality of first wire bonds and the metal clip at a side of the metal clip facing away from the semiconductor die. Additional semiconductor package embodiments and related methods of manufacture are also described.Type: GrantFiled: December 5, 2023Date of Patent: January 21, 2025Assignee: Infineon Technologies AGInventors: Mohd Kahar Bajuri, Joel Feliciano Del Rosario, Thai Kee Gan, Mohd Afiz Hashim, Mei Fen Hiew
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Patent number: 12199041Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.Type: GrantFiled: March 31, 2023Date of Patent: January 14, 2025Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yusheng Lin, Takashi Noma, Francis J. Carney
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Patent number: 12199150Abstract: A multi-level gate driver applied to the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) includes three parts: the SiC MOSFET information detection circuit, the signal level shifting circuit, and the segmented driving circuit. The SiC MOSFET information detection circuit includes the SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit. The segmented driving circuit includes a turn-on segmented driving circuit and a turn-off segmented driving circuit.Type: GrantFiled: June 24, 2022Date of Patent: January 14, 2025Assignee: University of Electronic Science and Technology of ChinaInventors: Zekun Zhou, Jianwen Cao, Yue Shi, Bo Zhang
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Patent number: 12176268Abstract: Embodiments disclosed herein include multi-die packages with open cavity bridges. In an example, an electronic apparatus includes a package substrate having alternating metallization layers and dielectric layers. The package substrate includes a first plurality of substrate pads and a second plurality of substrate pads. The package substrate also includes an open cavity between the first plurality of substrate pads and the second plurality of substrate pads, the open cavity having a bottom and sides. The electronic apparatus also includes a bridge die in the open cavity, the bridge die including a first plurality of bridge pads, a second plurality of bridge pads, and conductive traces. An adhesive layer couples the bridge die to the bottom of the open cavity. A gap is laterally between the bridge die and the sides of the open cavity, the gap surrounding the bridge die.Type: GrantFiled: March 24, 2020Date of Patent: December 24, 2024Assignee: Intel CorporationInventors: Omkar Karhade, Digvijay Raorane, Sairam Agraharam, Nitin Deshpande, Mitul Modi, Manish Dubey, Edvin Cetegen
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Patent number: 12170256Abstract: A method for fabricating a semiconductor product includes forming a dielectric layer over a top level metallization layer of a semiconductor process wafer. The dielectric layer is patterned using a grayscale mask process to define a contact pad opening in the dielectric layer, thereby producing a patterned dielectric layer in which the contact pad opening is aligned to a contact pad defined in the top level metallization layer. A metal layer is deposited over the patterned dielectric layer, including within the contact pad opening. A portion of the metal layer is removed by a chemical mechanical polishing (CMP) process, with a remaining portion of the metal layer having a sloped sidewall.Type: GrantFiled: August 27, 2021Date of Patent: December 17, 2024Assignee: Texas Instruments IncorporatedInventors: Sudtida Lavangkul, Yung Shan Chang
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Patent number: 12154858Abstract: Techniques are disclosed herein for connecting multiple chips using an interconnect device. In some configurations, one or more interconnect areas on a chip can be located adjacent to each other such that at least a portion of an edge of a first interconnect area is located adjacent to an edge of a second interconnect area. For example, an interconnect area can be located at a corner of a chip such that one or more edges of the interconnect area lines up with one or more edges of an interconnect area of another chip. The chip including at least one interconnect area can also be positioned and directly bonded to the interconnect device using other layouts, such as but not limited to a pinwheel layout. In some configurations more than one interconnect area can be included on a chip.Type: GrantFiled: June 18, 2020Date of Patent: November 26, 2024Assignee: Invensas LLCInventors: Javier A. Delacruz, Belgacem Haba
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Patent number: 12154956Abstract: Disclosed are a structure with a multi-level field plate and a method of forming the structure. The field plate includes multiple first conductors on a dielectric layer and separated from each other by spaces with different widths (e.g., by with progressively decreasing widths). A conformal additional dielectric layer extends over the first conductors and onto the dielectric layer within the spaces. The field plate also includes, on the additional dielectric layer, second conductor(s) with portions thereof extending into the spaces. Within the spaces, the second conductor portions are at different heights (e.g., at progressively increasing heights) above the dielectric layer. Such a field plate can be incorporated into a transistor (e.g., a high electron mobility transistor (HEMT)) to, not only reduce the peak of an electric field exhibited proximal to a gate terminal, but to ensure the electric field is essentially uniform level between the gate and drain terminals.Type: GrantFiled: April 11, 2024Date of Patent: November 26, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Johnatan Avraham Kantarovsky, Rajendran Krishnasamy, Mark D. Levy, John J. Ellis-Monaghan, Michael J. Zierak, Kristin Marie Welch
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Patent number: 12137620Abstract: A storage device 10 includes a phase change layer 40 containing tellurium, and a diffusion layer 50 containing at least one of germanium, silicon, carbon, tin, aluminum, gallium, and indium and disposed at a position adjacent to the phase change layer 40. The phase change layer 40 is capable of changing between a first state and a second state different from each other in electric resistance. The phase change layer 40 is in a crystal state in any of the first state and the second state. A length of the diffusion layer 50 in a direction orthogonal to a z direction is shorter than a length of the phase change layer 40 in the direction orthogonal to the z direction.Type: GrantFiled: December 13, 2021Date of Patent: November 5, 2024Assignee: Kioxia CorporationInventors: Kunifumi Suzuki, Yuuichi Kamimuta
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Patent number: 12136582Abstract: A power module is obtained in which the thermal resistance in the range from a semiconductor device to a base plate is reduced and the stress in the joining portion is relieved. The power module includes at least one semiconductor device, an insulating substrate having an insulating layer, a circuit layer provided on an upper surface of the insulating layer and a metal layer provided on a lower surface of the insulating layer, and a sintering joining member with an upper surface larger in outer circumference than a back surface of the at least one semiconductor device, to join together the back surface of the at least one semiconductor device and an upper surface of the circuit layer on an upper-surface side of the insulating layer.Type: GrantFiled: December 26, 2019Date of Patent: November 5, 2024Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yoshinori Yokoyama, Tetsu Negishi, Koji Yamazaki
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Patent number: 12125756Abstract: A semiconductor device in which even when cracks occur in a sealing material, the entry of moisture through the cracks can be prevented. A semiconductor device comprising a semiconductor element 11 mounted on a laminated substrate 12 and an electrically conductive connecting member, and a sealing material which seals the semiconductor element and the electrically conductive connecting member, wherein the sealing material includes a sealing layer 20 sealing members to be sealed including the laminated substrate 12, the semiconductor element 11, and the electrically conductive connecting member and including a thermosetting resin, and a protective layer 21 coating the sealing layer and including a silicone rubber, and wherein a value A1 of a tensile strength × elongation at break of the sealing layer 20 is less than a value A2 of a tensile strength × elongation at break of the protective layer 21, and the A2 is 1600 MPa or less.Type: GrantFiled: February 1, 2022Date of Patent: October 22, 2024Assignee: FUJI ELECTRIC CO., LTD.Inventor: Yuko Nakamata
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Patent number: 12112978Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a first chip comprising a first substrate, a first redistribution layer positioned above the first substrate, a first lower bonding pad positioned on the first redistribution layer, and a second lower bonding pad positioned above the first substrate and distant from the first lower bonding pad. The method also includes providing a second chip comprising a dense region and a loose region adjacent to the dense region; a plurality of upper pads positioned on the first lower bonding pad and the second lower bonding pad; and a plurality of second redistribution layers positioned on the plurality of upper pads. The method further performs bonding the second chip onto the first chip in a face-to-face manner, wherein the plurality of upper pads contact the first lower bonding pad and the second lower bonding pad.Type: GrantFiled: June 2, 2022Date of Patent: October 8, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Chun-Cheng Liao