Abstract: A semiconductor device package includes a substrate, a first insulation layer and an electrical contact. The first insulation layer is disposed on the first surface of the substrate. The electrical contact is disposed on the substrate and has a first portion surrounded by the first insulation layer and a second portion exposed from the first insulation layer, and a neck portion between the first portion and the second portion of the electrical contact. Further, the second portion tapers from the neck portion.

Abstract: An integrated circuit structure includes a substrate with a circuit region thereon and a copper interconnect structure disposed on the substrate. The copper interconnect structure includes an uppermost copper layer covered by a dielectric layer. An aluminum pad layer is provided on the dielectric layer. A metal layer is provided on the circuit region and is located between the uppermost copper layer and the aluminum pad layer.

Abstract: A semiconductor package includes: a semiconductor chip having an active surface, on which a connection pad is disposed, and an inactive surface opposite to the active surface; a heat-dissipating member disposed on the inactive surface of the semiconductor chip and including graphite; an encapsulant sealing at least a portion of each of the semiconductor chip and the heat-dissipating member; a capping metal layer disposed directly between the heat-dissipating member and the encapsulant; and a connection structure disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad, wherein the heat-dissipating member includes holes passing through at least a portion of the heat-dissipating member, and the holes overlap the inactive surface of the semiconductor chip.

Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

Abstract: The present disclosure provides a display substrate and a method for manufacturing the same and a display device. The display substrate includes: an array of sub-pixels, a signal line and a first retaining wall structure. A first conductive pattern of the signal line is between a base substrate and a second conductive pattern of the signal line. An orthographic projection of a second portion of the first retaining wall structure on the base substrate partially overlaps an orthographic projection of the first conductive pattern on the base substrate; a boundary of the orthographic projection of the second portion on the base substrate distal to the array of sub-pixels, is between the array of sub-pixels and a boundary of the orthographic projection of the first conductive pattern on the base substrate distal to the array of sub-pixels.

Abstract: An array substrate, a manufacturing method thereof, and a display panel are provided. The array substrate includes an active layer, a metal contact layer, a gate insulating layer, a gate layer, a source/drain layer, and a pixel electrode, which are sequentially disposed on a substrate. An insulating area of the metal contact layer corresponds to a channel area of the active layer, and a conductive area of the metal contact layer is disposed at two sides of the insulating area. A source and a drain of the source/drain layer are individually connected to the conductive area. Therefore, a problem of relatively high electrical resistance of a conductorized IGZO area in conventional TFT devices can be solved.

Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

Abstract: A semiconductor element is bonded to a circuit pattern integrated with an insulating layer and a heat radiation fin, a case is bonded to a peripheral edge of the heat radiation fin so as to surround the semiconductor element, the circuit pattern, and the insulating layer, and a sealing resin is sealed in a region surrounded by the insulating layer, the circuit pattern, and the case. An internal electrode includes a flat plate-shaped portion, and is provided with a through hole and a pair of bent and inclined-shaped support portions. The support portion is bonded to the circuit pattern, and the upper surface of the semiconductor element, the through hole, and an embossed portion provided around the through hole are bonded. The internal electrode, and an external electrode integrally molded with the case, are bonded.

Abstract: An electronic power module includes at least a semiconductor chip having at least one electronic power component and two metal layers between which the semiconductor chip is directly secured. At least a first of the two metal layers forms a redistribution layer having several distinct metal portions, each electrically connected to at least one electrical contact pad of the semiconductor chip, and/or at least one second of the two metal layers includes at least one first structured face arranged against the semiconductor chip and having at least one pad formed in a part of its thickness.

Abstract: A semiconductor device includes a substrate. A conductive layer is disposed on the substrate and extends in a first direction. An insulating layer is disposed on the conductive layer and exposes at least a portion of the conductive layer through a via hole. The via hole includes a first face extending in a first slope relative to a top face of the conductive layer. A second face extends in a second slope relative to the top face of the conductive layer that is less than the first slope. A redistribution conductive layer includes a first pad area disposed in the via hole. A line area at least partially extends along the first face and the second face. The first face directly contacts the conductive layer. The second face is positioned at a higher level than the first face in a second direction perpendicular to a top face of the substrate.

Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.

Abstract: A method of manufacturing a semiconductor package substrate includes forming a trench and a post by etching an upper surface of a base substrate including a conductive material, filling the trench with a resin, removing the resin exposed to outside of the trench such that an upper surface of the post and an upper surface of the resin are at same level, forming a conductive layer on an entire area of the upper surface of the post and the upper surface of the resin, and forming a circuit wiring including an upper circuit wiring and a lower circuit wiring by simultaneously patterning the conductive layer and a lower surface of the base substrate.

Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

Abstract: A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.

Abstract: An electronic component includes a semiconductor device including a semiconductor die including a first surface, the first surface including a first metallization structure and edge regions surrounding the first metallization structure, a second surface opposing the first surface and including a second metallization structure, and side faces extending between the first surface and the second surface, wherein the edge regions of the first surface and portions of the side faces are covered by a first polymer layer, wherein the electronic component further includes a plurality of leads and a plastic housing composition, wherein the first metallization structure is coupled to a first lead and the second metallization structure is coupled to a second lead of the plurality of leads.

Abstract: A semiconductor package includes a base substrate and an interposer substrate. The interposer substrate includes a semiconductor substrate, a first passivation layer, a wiring region, a through via penetrating through the semiconductor substrate and the first passivation layer, and a second passivation layer covering at least a portion of the first passivation layer and having an opening exposing a lower surface of the through via. The semiconductor package further includes a conductive pillar extending from the opening of the second passivation layer; and a conductive bump disposed between the conductive pillar and the base substrate. The opening of the second passivation layer has inclined side surfaces such that a width of the opening decreases towards the first passivation layer, and side surfaces of the conductive pillar are positioned to overlap the inclined side surfaces of the second passivation layer in a vertical direction.

Abstract: A method of attaching a metal clip to a semiconductor die includes: aligning a first bonding region of the metal clip with a first bond pad of the semiconductor die; and while the first bonding region of the metal clip is aligned with the first bond pad of the semiconductor die, forming a plurality of first wire bonds to the first bond pad of the semiconductor die through a plurality of openings in the first bonding region of the metal clip, the plurality of first wire bonds forming a joint between the metal clip and the first bond pad of the semiconductor die. Additional methods and related semiconductor packages produced from such methods are also described.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises an interposer, a first die attached to the interposer, and a second die attached to the interposer. In an embodiment, the electronic package further comprises a heatsink thermally coupled to the first die and the second die. In an embodiment, the heatsink has a first surface facing away from the first die and the second die and a second surface facing the first die and the second die. In an embodiment, the heatsink comprises a thermal break between the first die and the second die.

Abstract: The present application provides a semiconductor package with air gaps for reducing capacitive coupling between conductive features and a method for manufacturing the semiconductor package. The semiconductor package includes a first semiconductor structure and a second semiconductor structure bonded with the first semiconductor structure. The first semiconductor structure has a first bonding surface. The second semiconductor structure has a second bonding surface partially in contact with the first bonding surface. A portion of the first bonding surface is separated from a portion of the second bonding surface, a space between the portions of the first and second bonding surfaces is sealed and forms an air gap in the semiconductor package.

Abstract: A method includes forming a first passivation layer, forming a metal pad over the first passivation layer, forming a planarization layer having a planar top surface over the metal pad, and patterning the planarization layer to form a first opening. A top surface of the metal pad is revealed through the first opening. The method further includes forming a polymer layer extending into the first opening, and patterning the polymer layer to form a second opening. The top surface of the metal pad is revealed through the second opening.