Abstract: In a nonvolatile memory in which a load on a boosting circuit changes according to the number of rewrite bytes, the boosting circuit is configured so as to perform voltage boosting at a relatively slow predetermined speed regardless of the number of rewrite bytes, whereby stress applied to each storage element is reduced and rewrite resistance is enhanced.

Abstract: A memory including a plurality of memory cells, a sensing load, a reference load, a control circuit and a comparator. Each of the memory cells can store a bit data and provide a driving current according to the bit data. The sensing load is driven by the driving current and a driving voltage to generate a sensing voltage, and the reference load is driven by the driving voltage to generate a reference voltage. The control circuit can control the driving voltage to drive the sensing load or the reference load such that the sensing voltage or the reference voltage is kept constant while the driving current changes. The comparator is for comparing the sensing voltage with the reference voltage and therefore determining the bit data stored in the memory cell that provides the driving current.

Abstract: The present invention provides for variable-range hydrogen sensors and methods for making same. Such variable-range hydrogen sensors comprise a series of fabricated Pd—Ag (palladium-silver) nanowires—each wire of the series having a different Ag to Pd ratio—with nanobreakjunctions in them and wherein the nanowires have predefined dimensions and orientation. When the nanowires are exposed to H2, their lattace swells when the H2 concentration reaches a threshold value (unique to that particular ratio of Pd to Ag). This causes the nanobreakjunctions to close leading to a 6-8 orders of magnitude decrease in the resistance along the length of the wire and providing a sensing mechanism for a range of hydrogen concentrations.

Abstract: A method for controlling reading data that can increase the data transfer rate in an SDRAM of a posted CAS standard. A memory cell array is constituted by two sub-arrays that can be independently activated. When a READ command is received as an input one clock cycle after the input of an ACTV command, a row decoder activates only the sub-array containing the memory cell that is selected by a row address AX and column address AY, and then carries out the operations for reading data. The present invention thus reduces the areas that must be activated, thereby decreasing the load on the power supply and, when amplifying bit lines, shortening the time for the voltage of bit lines to attain the stipulated voltage. Consequently, the present invention increases the speed of reading data.

Abstract: A self-aligned oxide mask is formed utilizing differential oxidation rates of different materials. The self-aligned oxide mask is formed on a CVD grown base NPN base layer which compromises single crystal Si (or Si/SiGe) at active area and polycrystal Si (or Si/SiGe) on the field. The self-aligned mask is fabricated by taking advantage of the fact that poly Si (or Si/SiGe) oxidizes faster than single crystal Si (or Si/SiGe). An oxide film is formed over both the poly Si (or Si/siGe) and the single crystal Si (or Si/siGe) by using an thermal oxidation process to form a thick oxidation layer over the poly Si (or Si/siGe) and a thin oxidation layer over the single crystal Si (or Si/siGe), followed by a controlled oxide etch to remove the thin oxidation layer over the single crystal Si (or Si/siGe) while leaving the self-aligned oxide mask layer over the poly Si (or Si/siGe). A raised extrinsic base is then formed following the self-aligned mask formation.

Abstract: A non-volatile memory device and a fabrication method thereof, wherein a charge trapping layer, which is a memory unit, is formed at opposite ends of a gate of a cell, i.e., adjacent to source and drain junction regions, such that portions of the charge trapping layer adjacent to the source and drain junction regions are formed to be thicker than other portions of the charge trapping layer. Therefore, regions adjacent to junction regions function as electron storage regions and hole filing regions.

Abstract: A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.

Abstract: There are provided a semiconductor memory device and a data access method therefor, which can reduce current charged/discharged to bit lines because of charge recycling in order to improve the data holding characteristic of a cell capacitor and to reduce current consumption in stand-by mode. For the restore operation, a higher-voltage-side drive wire of the sense amplifier group is switched to a second voltage (V2). Charge stored in a recycling capacitor is used for charging bit lines from an equalizing voltage to the second voltage (V2). Next, the higher-voltage-side drive wire is switched from the second voltage (V2) to a first voltage (V1) so that a memory cell is restored. For the equalizing operation, the higher-voltage-side drive wire is switched to the second voltage (V2), and the charge in the bit lines is returned to the recycling capacitor. After that, the sense amplifying operation is terminated, and the bit line pair is shorted so as to be equalized to ½ of the second voltage (V2).

Abstract: According to the invention, a semiconductor component for the emission of electromagnetic radiation, especially light, is made that has the following features: an active layer for producing radiation, a p-type contact that is electrically connected to the active layer, an n-type contact that is electrically connected to the active layer, and a current-confining structure to define a current path, with the current-confining structure being provided between the n-type contact and the active layer.

Abstract: A nonvolatile semiconductor memory device comprises a memory cell array which includes memory cells and reference cells, the reference cells including a first reference cell and a second reference cell. A data judging control unit generates an average reference current based on a first reference current from the first reference cell and a second reference current from the second reference cell, and determines data of each of the memory cells by comparison of a read-out current of each memory cell with the average reference current. A control unit performs a program verification operation to each memory cell. A compensation current supplying unit supplies a compensation current to a bit line of a target memory cell when a leak current of a neighboring memory cell adjacent to the target memory cell exceeds a predetermined reference value during the program verification operation.

Abstract: A semiconductor memory apparatus is provided with a memory array, a first global bit line connected to a sense amplifier, a second global bit line connected to a write amplifier, and a selection circuit for connecting a plurality of bit lines selectively to the first global bit line and the second global bit line.

Abstract: A semiconductor nonvolatile memory in which read operations are carried out during write operations, includes: a core having a plurality of cell transistors for storing data; and a write verify circuit for detecting change in a core cell transistor's characteristic during a write operation in which the gate voltage/drain current characteristic of the cell transistor is changed to a condition corresponding to stored data by injecting a charge into or extracting a charge from the core cell transistor; and further includes a write verify inhibition signal generation circuit for generating a write verify inhibition signal in order to deactivate the write verify circuit during a read operation to the core cell transistor. The generation of a mistaken verify decision by the write verify circuit, due to a change in the power supply potential accompanying large current during a read operation, is prevented, as is malfunction of the write verify.

Abstract: A method for fabricating a capacitor on a semiconductor substrate is disclosed. The method may include simultaneously forming at least one via and at least one upper capacitor plate opening in a first dielectric layer having an underlying cap dielectric layer deposited over a first material region having a first conductive material within a conductive region and forming a trench above the via. The method may also include filling the via, trench, and upper capacitor plate opening with a second conductive material resulting in an integrated circuit structure and employing CMP to remove any excess second conductive material from the integrated circuit structure.

Abstract: An assembly includes a device for receiving at least one input to produce an output. An antenna supports the device to transfer the input to the device and further to transfer the output from the device such that the antenna supports a selected one of the input and the output as a high frequency current. The antenna includes a peripheral configuration which confines high frequency current to at least one dominant path to oscillate therein. The other one of the input and the output is a lower frequency signal present at least generally throughout the antenna. At least one port is positioned away from the dominant path to isolate the lower frequency signal from high frequency current in the dominant path. The antenna is configured to support the lower frequency signal having a frequency in a low frequency range including zero to several terahertz.

Abstract: A magnetic random-access memory (MRAM) cell according to an embodiment of the invention is disclosed that comprises a magnetic storage element having an easy axis and a hard axis, a write conductor positioned along one of the easy axis and the hard axis, and a write conductor positioned at a non-parallel and non-perpendicular angle to both of the easy axis and the hard axis.

Abstract: A method of manufacturing a semiconductor device includes forming a gate insulating film on a semiconductor substrate, forming a polysilicon layer on the gate insulating film, implanting ions into the polysilicon layer, patterning the polysilicon layer to form a gate electrode, annealing the gate electrode, and siliciding an upper portion of the gate electrode to form a silicide layer that has a lower portion facing the gate electrode and an upper portion opposite to the lower portion, the upper portion of the silicide layer being wider than the lower portion. A total dose of ions implanted during the step of implanting is 6×1015/cm2 or larger.

Abstract: A self-aligned dual-bit NVM cell. Each NVM cell has two isolated chargeable areas storing one bit respectively. That is, the two chargeable areas are physically separated. A control gate and a passivation layer are disposed over and between the two isolated chargeable areas. Moreover, the two isolated chargeable areas are formed by a self-alignment process.

Abstract: A semiconductor memory device as claimed in the present invention has a reference cell, a first memory cell, a second memory cell located nearer the first memory cell than the reference cell and a data read circuit provided therein. The data read circuit identifies first data stored in the first memory cell based on a reference cell electrical state of the reference cell and a first electrical state of the first memory cell. Furthermore, the data read circuit identifies second data stored in the second memory cell based on the first electrical state of the first memory cell and a second electrical state of the second memory cell. The semiconductor memory device having such configuration is able to suppress influence of variation in electrical performance of memory cell and stably identify data stored in a memory cell.

Abstract: A switching chip (101) using silicon as the base material is located on the upper surface of a cooling mechanism formed of a heat sink (115), an insulating substrate (114) and a conductive plate (108), with a first conductive layer (109A) sandwiched in between. Further, a diode chip (102) having a smaller area than a cathode electrode (103) and using a wide gap semiconductor as the base material is located on the cathode electrode (103) which has a smaller area than an anode electrode (105), with a second conductive layer (109B) sandwiched in between. A closed container (117) encloses every structural component except an exposed portion of a bottom surface (115BS) in the interior space.

Abstract: According to one aspect of the present invention, an apparatus is provided that includes a first global bit line, a second global bit line, a first block, a second block, and a reference cell array. The first block contains a first local bit line and a plurality of memory cells coupled to the first local bit line. The first local bit line can be selectively coupled to the first global bit line based upon a first control input. The second block contains a second local bit line and a plurality of memory cells coupled to the second local bit line. The second local bit line can be selectively coupled to the second global bit line based upon a second control input. The reference cell array contains a plurality of reference cells. The plurality of reference cells can be selectively coupled to either the first global bit line or the second global bit line based upon a third control input.