Abstract: A method for programming an NROM cell which includes the steps of applying a drain, a source and a gate voltage to the cell and verifying a programmed or a non-programmed state of the cell. If the cell is in the non-programmed state, the method includes the steps of increasing the drain voltage and maintaining the gate voltage at a constant level during at least a part of the step of increasing. The steps of applying, verifying, increasing and maintaining are repeated until the cell reaches the programmed state.

Abstract: In a non-volatile semiconductor memory device of the present invention, in the case of reading information from a second non-volatile memory element of an (i)-th twin memory cell and from a first non-volatile memory element of an (i+1)-th twin memory cell in the row direction, where i is an integer of not less than 1, the process senses an (i−1)-th bit line connecting with a first non-volatile memory element of the (i)-th twin memory cell, so as to detect an electric current running between the (i−1)-th bit line and an (i)-th bit line connecting with the second non-volatile memory element of the (i)-th twin memory cell, via the second non-volatile memory element of the (i)-th twin memory cell.

Abstract: In an FCRAM having a late write function, when a first command signal indicates “write active”, whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command signal indicates “write”, a write operation for a memory cell is performed by a late write scheme. When the second command signal indicates “auto-refresh”, an auto-refresh operation is performed. In the last write cycle of a write operation immediately preceding this auto-refresh operation, addresses for selecting a memory cell as an object of auto-refresh are predetermined. After data write to a memory cell is completed in the last write cycle, row precharge for auto-refresh is performed. After that, an auto-refresh operation (i.e., a data read operation and a data restore operation) is performed for the selected memory cell.

Abstract: A double capacity stacked memory device. In the present invention, two memory chips each have a plurality of control terminals and address terminals, and two data input/output terminals. The control terminals and address terminals of the first memory chip are electrically coupled to those of the second memory chip correspondingly to serve as control terminals and address terminals of the stacked memory respectively, and the data input/output terminals of the two memory chips construct four data input/output terminals of the stacked memory, such that the stacked memory accesses data in the first and second memory chip simultaneously according to an access command, and is thus suitable for double capacity memory devices in a standard package.

Abstract: The specification describes a DMOS transistor that is fully integrated with an electrostatic protection diode (ESD). The ESD diode is isolated from the DMOS device by a trench. The trench is metallized to tie the guard ring of the ESD to the substrate thereby increasing the current handling capabilities of the ESD. The trench also provides a convenient buried contact to the RF ground.

Abstract: A semiconductor device, capable of precluding the deterioration of flatness and electrical properties due to the non-planarized topology and enhancing oxidative endurance and the process margins, which includes a conductive layer, an insulated layer formed on the conductive layer, a glue layer formed on the insulating layer, a connection unit, which is in contact with the conductive layer through the glue layer and the insulating layer and whose surface is planarized with that of the glue layer and a capacitor including a first electrode formed on the connection unit and the glue layer, a dielectric layer formed on the first electrode and a second electrode formed on the dielectric layer.

Abstract: A PBGA package is provided. The heat spreader interfaces with the substrate with the standoff of the heat spreader. The stand-off of the heat spreader is provided with an opening, the stand-off of the heat spreader is aligned with the substrate of the PBGA package by means of a copper pad that is provided over a second surface of the substrate. A solder bump is further provided over the surface of the copper pad. Thermally conductive solder is deposited over the opening of the heat spreader and over the copper pad. If the heat spreader stand-off is aligned with contact pads, thermally conductive epoxy is deposited over the contact pads.

Abstract: A magnetic recording medium improved in spacing loss and durability is disclosed. The magnetic recording medium is composed so that a magnetic layer is formed on a non-magnetic support, further thereon a non-magnetic protective layer having projected portions formed thereon in a discrete manner according to a thickness distribution, and further thereon a lubricant layer is formed so as to produce surface projections. In other words, the projected portions are formed in a discrete manner to the non-magnetic protective layer formed on the magnetic layer, where the non-magnetic protective layer is principally intended for the purpose of rust prevention or the like for the magnetic layer. The whole portion of the non-magnetic protective layer inclusive of the projected portions is composed with the same material.

Abstract: An improved silicon building block is disclosed. In an embodiment, the silicon building block has at least two vias through it. The silicon building block is doped and the vias filled with a first material, and, optionally, selected ones of the vias filled instead with a second material. In an alternative embodiment, regions of the silicon building block have metal deposited on them.

Abstract: The present invention is related to a single ended sense amplifier, which is engaged in receiving signals of a memory apparatus of a semiconductor, and generates output signals in an output terminal. The single ended sense amplifier comprises: a first loading unit, which offers a loading current; a first sense switch unit, which is in between a memory apparatus of semiconductor and the first loading unit to couple them together, and connects to the first loading unit to form an output terminal in order to be as a channel switch for a channel from semiconductor memory apparatus to the output terminal of the sense amplifier; a second loading unit, which offers a charging current; a second sense switch unit, which is in between the semiconductor memory apparatus and the second loading unit to couple them together; an inverse logic unit, which is among the semiconductor memory apparatus, the first sense switch unit and the second sense switch unit for controlling the plural sense switch units.

Abstract: System for using a dynamic reference cell in a double-bit cell memory. A method is provided for reading and verifying a double bit core cell in a memory device. The memory device includes a dynamic reference cell and a fixed reference cell. The method comprises the steps of programming the dynamic reference cell using the fixed reference cell, and programming the double bit core cell using the dynamic reference cell. When the dynamic reference cell is located along with the core cell on the same word line, a constant current source added to a core cell data line operates during program verify to provide a current difference between the core cell and the dynamic reference cell.

Abstract: A memory device includes delay locked loop that generates an internal signal based on an external signal. The internal signal serves a reference clock signal for most modes operations of the memory device. In a self refresh mode, the delay locked loop is completely deactivated to completely deactivate the internal signal. In a non-self refresh mode, the delay locked loop is periodically deactivated to periodically deactivate the internal signal based on certain modes of operations of the memory device.

Abstract: A method for forming a vertical nitride read-only memory cell. A substrate having at least one trench is provided. A first conductive layer is formed in the lower trench and insulated from the substrate to serve as a source line. A first doping region is formed in the substrate adjacent to the top of the first conductive layer. A first insulating layer is formed on the first conductive layer. A second doping region is formed in the substrate adjacent to the top of the trench. A second insulating layer is formed over the sidewall of the trench and on the first insulating layer to serve as a gate dielectric layer. A second conductive layer is formed in the upper trench to serve as a control gate. A vertical nitride read-only memory cell is also disclosed.

Abstract: A memory cell of SRAM includes: two N-channel MOS transistors connected in series between a first storage node and a line of a ground potential and two N-channel MOS transistors connected in series between a second storage node and a line of a ground potential. Since no storage data is inverted unless one &agr;-particle passes through two N-channel MOS transistors, a soft error hard to occur.

Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

Abstract: A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

Abstract: To provide a ferroelectric storage device which can read all the quantities of charge (polarization quantity: 2Pr) accumulated in a ferroelectric during a writing operation. In the present invention, a bit line is recharged, a charge quantity required for recharging is detected, and the quantity is read on a sub bit line, thereby achieving a stable reading operation.

Abstract: Techniques for producing and utilizing temperature compensated voltages to accurately read signals (e.g., voltages) representing data stored in memory cells of a memory system are disclosed. The memory system is, for example, a memory card. The magnitude of the temperature compensation can be varied or controlled in accordance with a temperature coefficient. These techniques are particularly well suited for used with memory cells that provide multiple levels of storage.

Abstract: A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOB transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOB transistors is in-creased, the threshold voltage of the MOB transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOB transistor can be set to 1, thereby allowing a reduction in the memory cell area.

Abstract: A method for generating an initializing signal capable of preventing inner circuits installed in a semiconductor memory device from being initially unstably operated due to the application of external electric power. The method includes the steps of: (a) receiving a precharge command for precharging the semiconductor memory device; (b) activating the initializing signal to a first level in response to the received precharge command; (c) receiving a refresh command for refreshing the semiconductor memory device after receipt of the precharge command; (d) receiving a mode set command for setting an operational mode of the semiconductor memory device after receipt of the refresh command; and (e) deactivating the initializing signal to a second level in response to the received mode set command.