Abstract: The invention includes an apparatus and a method that provides a memory back-up system. The memory back-up system includes a first memory cell, and a non-volatile memory cell that is interfaced to the first memory cell. Control circuitry allows data to be written to either the first memory cell or the non-volatile memory cell, and provides transfer of the data from either the first memory cell or the non-volatile memory cell, to the other of either the first memory cell or the non-volatile memory cell. The memory back-up system can also include a plurality of first memory cells, and a plurality of non-volatile memory cells that are interfaced to the first memory cells. Control circuitry allows data to be written to either the first memory cells or the non-volatile memory cells, and that provides transfer of the data from either the first memory cells or the non-volatile memory cells, to the other of either the first memory cells or the non-volatile memory cells.

Abstract: Methods of producing an electromechanical circuit element are described. A lower structure having lower support structures and a lower electrically conductive element is provided. A nanotube ribbon (or other electromechanically responsive element) is formed on an upper surface of the lower structure so as to contact the lower support structures. An upper structure is provided over the nanotube ribbon. The upper structure includes upper support structures and an upper electrically conductive element. In some arrangements, the upper and lower electrically conductive elements are in vertical alignment, but in some arrangements they are not.

Abstract: A pre-formed integrated circuit chip is encapsulated into an electronic package, by forming an interconnect assembly separately from the pre-formed integrated circuit chip. If the interconnect assembly tests good it is bonded to the prepared integrated circuit chip. The interconnect assembly is flip bonded to the chip. The interconnect assembly and chip are passivated or potted into an integral structure to provide the electronic package. At least one test pad is defined in an interconnect layer, which test pad can be accessed and electrically connected on opposing sides of the test pad. The chip is underfilled with an insulating material to remove all voids between the chip and the interconnect assembly. The integrated circuit chip is then thinned. The test pad is accessed to test the chip. A plurality of interconnect assemblies and chips are bonded together to form a corresponding plurality of electronic packages.

Abstract: A simultaneous operation flash memory chip architecture having a flexible memory bank partition for forming first and second memory banks from a plurality of flash memory arrays, said partition being defined by selecting one of a plurality of preformed metal masks, which allows the formation and extension of pre-decoded address lines to inputs of decoders associated with the first and second memory banks, respectively.

Abstract: A non-volatile memory device includes floating gate memory cells, a pulse counter and voltage pump control circuitry. The control circuitry selectively activates pumps in response to a count output of the counter. In one embodiment, the pump output current is increased as the counter output increases. The memory allows for erase operations that reduce leakage current during initiation of an erase operation.

Abstract: A semiconductor memory device is provided including plural memory cells and capable of a dual port access. In the memory device the memory cell is composed with two driver transistors 1, two load transistors 2, and two access transistors 3, and in the data read, the word line 11 makes the access transistors 3 conductive to read out data held in the driver transistors to a pair of the bit lines, and in the data write, the load transistor control line makes the load transistors conductive to write data into the driver transistors from a pair of the memory cell VCC lines.

Abstract: The MRAM semiconductor memory configuration has MRAM main cell arrays in the form of a crosspoint array or a transistor array together with redundant MRAM cell arrays formed of redundant MRAM memory cells arranged in a plurality of planes and provided on the same chip. The redundant MRAM cell arrays are distributed over the individual planes of the memory matrix or one plane of the memory array is used in its entirety for providing redundant cell arrays.

Abstract: A semiconductor memory including an address change detection unit for detecting a change of an address and outputting an address change detection signal, a selection unit for selectively switching the polling data and the read data by a polling signal, and outputting its data to the output buffer, and a delay unit for inhibiting the polling signal from being transferred to the selection unit while the address change detection signal is activated. When the polling signal changes while a sense amplifier senses data, the logic level of a signal output from the output buffer is inhibited from being changed. This prevents any malfunction caused by output noise generated during the data sense operation of the sense amplifier.

Abstract: A semiconductor storage device conducts a late-write operation. The semiconductor storage device comprises: a memory core circuit storing data; a data latch circuit storing preceding data corresponding to a preceding write-operation; an address compare circuit comparing a preceding address corresponding to the preceding write-operation and a present address corresponding to a present read-operation so as to determine whether the preceding address and the present address match each other; and a control circuit. The control circuit controls a test read-operation to read data from the memory core circuit regardless of whether the preceding address and the present address match each other.

Abstract: A memory architecture especially adapted to provide an architecture to house one or more TCCT-based memory cells and to provide a reference signal. The memory architecture is designed to effectively resolve stored information from memory cells into logical values, such as logical “0” and “1.” An exemplary memory architecture includes a data block that comprises a first set of one or more bit lines, where a word line one line extends to a first subset of the first set of the one or more bit lines. The data block also includes a word line two line extending to a second subset of the first set of the one or more bit lines. A memory cell is coupled to the word line one line, the word line two line and a common bit line of the first and second subsets of bit lines.

Abstract: A semiconductor memory device comprises a write column select line or read column select line for shielding a signal line. The semiconductor memory device may include a signal line, a read column select line, and a write column select line. The signal line may transmit an operation signal related to the operation of the semiconductor memory device. The read column select line may transmit a read column select signal, which may control transfer of a data signal of a bit line to a data line. The write column select line may transmit a write column select signal, which may control transfer of the data signal of the data line to the bit line. One of the read column select line and the write column select line to transmit a deactivated column select signal among the read column select signal and the write column select signal, may be maintained at a predetermined logic level and may shield the signal line.

Abstract: Power to operates memory bank of DRAM stably is supplied with reduced power consumption. A semiconductor storage unit includes multiple arrays forming memory banks on a substrate, first and second power supplies. Multiple arrays are arranged like a matrix and surround the central region of the substrate. Each memory bank consists of two of the multiple arrays. Each first power supply supplies driving power to a peripheral circuit which drives each multiple array. Second power supplies are arranged at four corners of the central region, each supply provides access power to word lines which access the multiple arrays. The first power supplies are mounted to a central and the opposite side for predetermined arrays, serve as a main and an auxiliary power supply to provide main and auxiliary power (smaller than the main power), and provide distantly arranged two of the multiple arrays forming a memory bank with power.

Abstract: To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.

Abstract: A method of reading a memory cell, and a memory array using the method, are described. An electrical load is applied to a first node in the memory array, the first node corresponding to the memory cell. A second node in the memory array, the second node on a same word line as the first node, is precharged. The second node is separated from the first node by at least one intervening node in the same word line.

Abstract: A semiconductor device (200) that includes a semiconductor substrate (210), semiconductor features (230, 235, 240, 260) located thereover and an insulating photoconductive layer (270) coupling the semiconductor features (230, 235, 240, 260). The photoconductive layer (270) is configured to provide conductivity between the semiconductor features (230, 235, 240, 260) in a presence of a plasma.

Abstract: A semiconductor memory device performs a normal boost operation and increases access speed of the operation. The semiconductor memory device includes: a plurality of memory cells; a plurality of word lines to which voltages are applied to select the plurality of memory cells; a decoder that selects one of the plurality of word lines based on an address signal representing an address of one of the plurality of memory cells to be accessed; a control circuit that outputs an activated control signal and an deactivated control signal according to a transition of the address signal; and a booster that has a plurality of booster circuits including first booster circuit and second booster circuit. The first booster circuit is connected to the decoder and supplies boosted voltage to a selected word line based on the activated control signal. The second booster circuit is input the deactivated control signal.

Abstract: A NOR-type flash memory device includes a global decoder circuit that is coupled to global wordlines. The global decoder circuit drives the global wordlines using wordline voltages that will be applied to local wordlines in each operation mode, and has wordline select switches each corresponding to the global wordlines. A local decoder circuit couples the local wordlines to the global wordlines in response to a sector select signal, and a sector generates a control signal in accordance with address information for selecting a memory cell array. A switch circuit includes a plurality of depletion MOS transistors each being coupled between corresponding first and second wordline. The depletion MOS transistors are commonly controlled by a control signal. Each of the wordline select switches is made of two NMOS transistors.

Abstract: An object of the invention is to obtain a memory array capable of preventing coupling noise from being produced on a cell plate voltage line. A memory array of the invention comprises: first and second dummy word lines (DWL0 and DWL1); a first dummy memory cell (DMC0) connected to a first bit line (BL), the first dummy word line (DWL0) and a common cell plate voltage line (VL); and a second dummy memory cell (DMC1) connected to a second bit line (BLB), the second dummy word line (DWL1) and the voltage line (VL), wherein second dummy data having opposite polarity to polarity of first data are written in the second dummy memory cell (DMC1) so as to write the first data in a first memory cell (MC0), and first dummy data having opposite polarity to polarity of second data are written in the first dummy memory cell (DMC0) so as to write the second data in a second memory cell (MC1).

Abstract: The bit line overdrive circuit of the present invention comprises a VBLH potential generation circuit generating a bit line final potential relative to a VBLH power supply line for driving a sense amplifier, a charge adjusting capacitance C, a transistor for supplying an overdrive potential to the VBLH power supply line, and a transistor for connecting a PCS node to the VBLH power supply line. The charge pre-charged from the overdrive potential to the VBLH power supply line is shared among the capacitance of the above-noted circuit elements connected to the VBLH power supply line, the bit line capacitance, and the capacitance of a cell capacitor so as to form a VBLH power supply of a substantially one system, thereby avoiding the generation of a power supply noise caused by the power supply switching.

Abstract: A semiconductor memory capable of reducing refresh cycle time, which includes normal memory cells provided at predetermined intersections of plural normal word lines and plural bit lines, and redundant memory cells of redundant word lines and the plural bit lines, a redundancy relief circuit evaluates whether each of an internal address signal for a memory operation and a refresh address signal corresponds to the address of a defective word line of the plural normal word lines. An address selecting circuit switches the defective word line to a redundant word line according to the evaluation result. The redundancy relief circuit then evaluates whether a refresh address added to the refresh address signal corresponds to a defective address, and during refresh, the address selecting circuit selects a normal or redundant word line according to the evaluation result in a preceding cycle.