Patents Examined by Hoai Pham
  • Patent number: 7344940
    Abstract: Integrated circuit ferroelectric memory devices are provided that include an integrated circuit transistor. The memory device further includes a ferroelectric capacitor on the integrated circuit transistor. The ferroelectric capacitor includes a first electrode adjacent the transistor, a second electrode remote from the transistor and a ferroelectric film therebetween. The memory device further includes a plate line directly on the ferroelectric capacitor. Methods are also provided that include forming a ferroelectric capacitor on the integrated circuit transistor and forming a plate line directly on the ferroelectric capacitor.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: March 18, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Ho Kim, Ki-Nam Kim
  • Patent number: 7315046
    Abstract: A semiconductor light-emitting device has a pair of leads placed in parallel, a light-emitting element on the upper end of one lead, a bonding wire for electrically connecting the semiconductor light-emitting element of the upper end of another lead, and an envelope formed from a light-transmitting resin for sealing the semiconductor light-emitting element, the bonding wire, and the upper end of the leads, provided with a non-circular lateral cross-sectional surface structure with a long axis and a short axis. In the device, when observed along a direction in which the plurality of light-emitting devices are mounted on a same lead frame, a curvature of the lateral direction of said envelope is smaller than a curvature of the vertical direction of said envelope.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: January 1, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Komoto, Toshiaki Tanaka, Norio Fujimura
  • Patent number: 7315045
    Abstract: The present invention relates to a sapphire/gallium nitride laminate, wherein a curvature radius thereof is positioned on the right side of a first curve plotted from the following functional formula (I): Y=Y0+A·e?(x?1)/T??(I) wherein Y is the curvature radius (m) of a sapphire/gallium nitride laminate, X is the thickness (?m) of a gallium nitride film, Y0 is 5.47±0.34, A is 24.13±0.50, and T is 0.56±0.04. The inventive laminate can be advantageously used in the manufacture of a high quality electronic device.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: January 1, 2008
    Assignee: Samsung Corning Co., Ltd.
    Inventors: Chang Ho Lee, Hae Yong Lee, Choon Kon Kim
  • Patent number: 7312516
    Abstract: A dense semiconductor flip-chip device assembly is provided with a heat sink/spreading/dissipating member that is formed as a paddle of a metallic paddle frame in a strip of paddle frames. Semiconductor dice are bonded to the paddles by, e.g., conventional semiconductor die attachment methods, enabling bump attachment and testing to be conducted before detachment from the paddle frame strip.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: December 25, 2007
    Assignee: Micron Technology, Inc.
    Inventor: David J. Corisis
  • Patent number: 7304389
    Abstract: A semiconductor device includes a semiconductor element, a resin substrate where the semiconductor element is mounted, and a supporting plate configured to support the resin substrate. A first gas discharging hole is made through the supporting plate. Gas generated from the resin substrate is discharged through the first gas discharging hole.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: December 4, 2007
    Assignee: Fujitsu Limited
    Inventor: Hideaki Yoshimura
  • Patent number: 7302671
    Abstract: An integrated circuit (IC) including at least one combinational logic path. The features in the combinational logic path are self compensating for out-of-focus effects. In particular, field effect transistor (FET) gates may be iso-focally spaced such that the gate (critical dimension) may move with changing focus, but the gate length remains the same. Alternately, logic circuits in a path may self-compensate for focus effects on individual circuits.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: November 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Fook-Luen Heng, Jin-Fuw Lee, Daniel L. Ostapko
  • Patent number: 7301187
    Abstract: Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92?) serially located between the channel (90) and the source (70, 70?) or drain (76, 76?). A buried region (96, 96?) of the same conductivity type as the drift space (92, 92?) and the source (70, 70?) or drain (76, 76?) is provided below the drift space (92, 92?), separated therefrom in depth by a narrow gap (94, 94?) and ohmically coupled to the source (70, 70?) or drain (76, 76?). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94?).
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: November 27, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Edouard D. Defresart, Richard J. Desouza, Xin Lin, Jennifer H. Morrison, Patrice M. Parris, Moaniss Zitouni
  • Patent number: 7297999
    Abstract: An interlayer insulating film (22) is formed on a semiconductor substrate. A conductive plug (25) is embedded in a via hole formed through the interlayer insulating film. An oxygen barrier conductive film (33) is formed on the interlayer insulating film and being inclusive of an area of the conductive plug as viewed in plan. A capacitor (35) laminating a lower electrode, a dielectric film and an upper electrode in this order is formed on the oxygen barrier film. An intermediate layer (34) is disposed at an interface between the oxygen barrier film and the lower electrode. The intermediate layer is made of alloy which contains at least one constituent element of the oxygen barrier film and at least one constituent element of the lower electrode.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: November 20, 2007
    Assignee: Fujitsu Limited
    Inventor: Wensheng Wang
  • Patent number: 7297596
    Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: November 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Sam Lee, Yong-Tae Kim, Mi-Youn Kim, Gyo-Young Jin, Dae-Won Ha, Yun-Gi Kim
  • Patent number: 7297984
    Abstract: A semiconductor light-emitting device has a pair of leads placed in parallel, a light-emitting element on the upper end of one lead, a bonding wire for electrically connecting the semiconductor light-emitting element of the upper end of another lead, and an envelope formed from a light-transmitting resin for sealing the semiconductor light-emitting element, the bonding wire, and the upper end of the leads, provided with a non-circular lateral cross-sectional surface structure with a long axis and a short axis. In the device, when observed along a direction in which the plurality of light-emitting devices are mounted on a same lead frame, a curvature of the lateral direction of said envelope is smaller than a curvature of the vertical direction of said envelope.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: November 20, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Komoto, Toshiaki Tanaka, Norio Fujimura
  • Patent number: 7291879
    Abstract: The present invention provides a semiconductor memory device which comprises an interlayer insulating film formed on a semiconductor substrate, a contact plug formed in the interlayer insulating film and having one end electrically connected to the semiconductor substrate, a ferroelectric capacitor formed on the interlayer insulating film and comprising a first electrode, a ferroelectric film and a second electrode electrically connected to the other end of the contact plug, an insulating film which covers the ferroelectric capacitor and has an opening that exposes the first electrode, and a wiring film which covers the ferroelectric capacitor and the insulating film and is electrically connected to the first electrode exposed through the opening and which consists of a material having conductivity and even a hydrogen diffusion preventing function.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: November 6, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Toshio Ito
  • Patent number: 7288820
    Abstract: Systems and methods are described for a low-voltage electrostatic discharge clamp. A resistor pwell-tied transistor may be used as a low-voltage ESD clamp, where the body of the transistor is coupled to the source by a resistor, thereby reducing a DC leakage current and minimizing latch-ups in the transistor while maintaining effective ESD performance.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: October 30, 2007
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Baird, Richard T. Ida, James D. Whitfield, Hongzhong Xu, Sopan Joshi
  • Patent number: 7288790
    Abstract: A TFT array panel includes: first and second gate members connected to each other; a gate insulating layer formed on the first and the second gate members; first and second semiconductor members formed on the gate insulating layer opposite the first and the second gate members, respectively; first and second source members connected to each other and located near the first and the second semiconductor members, respectively; first and second drain members located near the first and the second semiconductor members, respectively, and located opposite the first and the second source members with respect to the first and the second gate members, respectively; and a pixel electrode connected to the first and the second drain members. The first gate, semiconductor, source, and drain members form a first TFT, and the second gate, semiconductor, source, and drain members form a second TFT.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: October 30, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Mi Tak, Seung-Soo Baek, Joo-Ae Youn, Dong-Gyu Kim
  • Patent number: 7288795
    Abstract: A semiconductor light-emitting device has a pair of leads placed in parallel, a light-emitting element on the upper end of one lead, a bonding wire for electrically connecting the semiconductor light-emitting element of the upper end of another lead, and an envelope formed from a light-transmitting resin for sealing the semiconductor light-emitting element, the bonding wire, and the upper end of the leads, provided with a non-circular lateral cross-sectional surface structure with a long axis and a short axis. In the device, when observed along a direction in which the plurality of light-emitting devices are mounted on a same lead frame, a curvature of the lateral direction of said envelope is smaller than a curvature of the vertical direction of said envelope.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: October 30, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Komoto, Toshiaki Tanaka, Norio Fujimura
  • Patent number: 7285462
    Abstract: A DRAM is provided that can reduce the parasitic capacitance between trench-type stacked cell capacitors in a memory cell region and suppress malfunction caused by noise. The trench-type stacked cell includes a number of capacitors having the same shape. The capacitors are formed in such a manner that storage nodes, a capacitor insulating film, and a plate electrode are buried in each of a plurality of trenches of an interlayer insulating film. The cell layout can be as follows: the capacitors are arranged so that only a part of a side face of one trench is opposite to that of the other; the capacitors are arranged so that the side face of one trench is opposite completely to that of the other and the distance between the opposing side faces is larger at the central portions of the respective trenches; or the cell is arranged so that the plate electrode is buried in a concavity between the cell capacitors.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: October 23, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yoshiyuki Shibata
  • Patent number: 7285838
    Abstract: A semiconductor device includes a first n-type source/drain region 48a and a second p-type source/drain region 48b formed on a semiconductor substrate 20 away from side surfaces of first and second gate electrodes 39a, 39b at a first interval W4 respectively, a second n-type source/drain region 48c and a first p-type source/drain region 48d formed on the semiconductor substrate 20 away from side surfaces of third and fourth gate electrodes 39c, 39d at a second interval W3, which is wider than the first interval W4, respectively, and third and fourth insulating sidewalls 43c, 43d extended onto source/drain extensions 42c, 42d on both sides of third and fourth gate electrodes 39c, 39d from edges of upper surfaces of the third and fourth gate electrodes 39c, 39d respectively.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: October 23, 2007
    Assignee: Fujitsu Limited
    Inventors: Narumi Ohkawa, Masaya Katayama
  • Patent number: 7282756
    Abstract: Structurally-stable, tall capacitors having unique three-dimensional architectures for semiconductor devices are disclosed. The capacitors include monolithically-fabricated upright microstructures, i.e., those having large height/width (H/W) ratios, which are mechanical reinforcement against shear forces and the like, by a brace layer that transversely extends between lateral sides of at least two of the free-standing microstructures. The brace layer is formed as a microbridge type structure spanning between the upper ends of the two or more microstructures.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: October 16, 2007
    Assignee: Micron Technology Inc.
    Inventors: Vishnu K. Agarwal, Gurtej Sandhu
  • Patent number: 7282407
    Abstract: A semiconductor memory device and method of manufacturing a semiconductor memory device that prevents oxidation of the bit lines caused by misalignment which may occur when patterning a storage electrode. An oxidation preventing layer, such as a nitride layer, is formed over the bit lines or in the contact holes to eliminate the diffusion of oxygen into the bit line structure, thereby preventing oxidation of the bit lines.
    Type: Grant
    Filed: June 29, 1998
    Date of Patent: October 16, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-woo Park, Jun-yong Noh, Bon-young Koo, Chang-jin Kang, Chul Jung, Seok-woo Nam
  • Patent number: 7279796
    Abstract: A microelectronic die is provided having an integrated thermoelectric module. The microelectronic die has a die substrate, a microelectronic circuit formed on a front side of the die substrate, and the thermoelectric module on a backside of the die substrate. Vias in the substrate interconnect the thermoelectric module with power and ground planes on the front side of the die substrate.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: October 9, 2007
    Assignee: Intel Corporation
    Inventors: Chuan Hu, Gregory M. Chrysler, Ravi V. Mahajan
  • Patent number: 7276785
    Abstract: The invention relates to an electronic module having electronic components, which are arranged in vertically staggered component layers, which are electrically conductively connected to one another via regions, which are uncovered within the respective component layers, of contact bumps or of bonding connections and via interconnects, which are arranged between the component layers and are connected to the uncovered regions. Moreover, the invention relates to a process for producing the electronic module, either in a panel or as individual components.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: October 2, 2007
    Assignee: Infineon Technologies AG
    Inventors: Michael Bauer, Wolfram Eurskens, Gerold Gruendler, Rudolf Kerler, Heinz Pape, Peter Strobel