Abstract: An interconnect structure for use in an integrated circuit is provided. The interconnect structure includes a first low-K dielectric material. The first low-K material may be modified with a first group of carbon nanotubes (CNTs) and disposed on a metal line. The first low-K material is modified by dispersing the first group of CNTs in a solution, spinning the solution onto a silicon wafer and curing the solution to form the first low-K material modified with the first CNTs. The metal line includes a top layer and a bottom layer connected by a metal via. The interconnect structure also includes a second low-K dielectric material modified with a second group of CNTs and disposed on the bottom layer. Accordingly, embodiments the present disclosure could help to increase the mechanical strength of the low-K material or the entire interconnect structure.

Abstract: An active matrix substrate (20a) includes a plurality of pixel electrodes (18a) arranged in a matrix, and a plurality of TFTs (5) each connected to a corresponding one of the pixel electrodes (18a), and each including a gate electrode (11a) provided on an insulating substrate (10a), a gate insulating film (12a) covering the gate electrode (11a), a semiconductor layer (16a) provided on the gate insulating film (12a) and having a channel region (C) overlapping the gate electrode (11a), and a source electrode (15aa) and a drain electrode (15b) of copper or copper alloy provided on the gate insulating film (12a) and separated from each other by the channel region (C) of the semiconductor layer (16a). The semiconductor layer (16a) is formed of an oxide semiconductor and covers the source electrode (15aa) and the drain electrode (15b).

Abstract: A HEMT comprising a plurality of active semiconductor layers formed on a substrate. Source electrode, drain electrode, and gate are formed in electrical contact with the plurality of active layers. A spacer layer is formed on at least a portion of a surface of said plurality of active layers and covering the gate. A field plate is formed on the spacer layer and electrically connected to the source electrode, wherein the field plate reduces the peak operating electric field in the HEMT.

Abstract: The invention relates to an antenna unit for wireless communication to a multitude of wireless interfaces comprising a multitude of individual antennas, each antenna comprising a coil comprising at least one winding and the individual antennas embrace the same volume and to a hearing aid comprising such antenna unit. The object of the present invention is to provide an antenna unit and a hearing aid providing several wireless interfaces at a relatively small volume. The problem is solved in that at least one of the coils is adapted for providing an inductive coupling to another device. Among the advantages are reduced space/volume, reduced cost and reduced sensitivity to production tolerances compared to a solution comprising individual, separate antennas. The invention may e.g. be used in wireless communication devices, e.g. mobile telephones, head phones, head sets, hearing aids, etc.

Abstract: A semiconductor device, which exhibits an increased design flexibility for a capacitor element, and can be manufactured with simple method, is provided. A semiconductor device 100 includes: a silicon substrate 101; an interlayer film 103 provided on the silicon substrate 101; a multiple-layered interconnect embedded in the interlayer film 103; a flip-chip pad 111, provided so as to be opposite to an upper surface of an uppermost layer interconnect 105 in the multiple-layered interconnect and having a solder ball 113 for an external coupling mounted thereon; and a capacitance film 109 provided between said uppermost layer interconnect 105 and the flip-chip pad 111. Such semiconductor device 100 includes the flip-chip pad 111 composed of an uppermost layer interconnect 105, a capacitive film 109 and a capacitor element 110.

Abstract: Embodiments of the present invention relate to an improved package for a bi-directional and reverse blocking battery switch. According to one embodiment, two switches are oriented side-by-side, rather than end-to-end, in a die package. This configuration reduces the total switch resistance for a given die area, often reducing the resistance enough to avoid the use of backmetal in order to meet resistance specifications. Elimination of backmetal reduces the overall cost of the die package and removes the potential failure modes associated with the manufacture of backmetal. Embodiments of the present invention may also allow for more pin connections and an increased pin pitch. This results in redundant connections for higher current connections, thereby reducing electrical and thermal resistance and minimizing the costs of manufacture or implementation of the die package.

Abstract: The present invention discloses a floating gate structure of a flash memory device and a method for fabricating the same, which relates to a nonvolatile memory in a manufacturing technology of an ultra-large-scaled integrated circuit. In the invention, by modifying a manufacturing of a floating gate in the a standard process for the flash memory, that is, by adding three steps of deposition, two steps of etching and one step of CMP, an -shaped floating gate is formed. In addition to these steps, all the other steps are the same as those of the standard process for the flash memory process. By the invention, a coupling ratio may be improved effectively and a crosstalk between adjacent devices may be lowered, without adding additional photomasks and barely increasing a process complexity, which are very important to improve programming speed and reliability.

Abstract: A non-volatile memory device is disclosed having a charge storage layer that incorporates a plurality of nano-crystals. A substrate having a source region and a drain region is provided. Select and control gates are formed on the substrate. The charge storage layer is provided between the control gate and the substrate. The nano-crystals in the charge storage layer have a size of about 1 nm to about 10 nm, and may be formed of Silicon or Germanium. Writing operations are accomplished via hot electron injection, FN tunneling, or source-side injection. Erase operations are accomplished using FN tunneling. The control gate is formed of a single layer of polysilicon, which reduces the total number of processing steps required to form the device, thus reducing cost.

Abstract: A semiconductor device includes stacked-gate structures including a plurality of cell gate patterns and insulating patterns alternately stacked on a semiconductor substrate and extending in a first direction. Active patterns and gate dielectric patterns are disposed in the stacked-gate structures. The active patterns penetrate the stacked-gate structures and are spaced apart from each other in a second direction intersecting the first direction, and the gate dielectric patterns are interposed between the cell gate patterns and the active patterns and extend onto upper and lower surfaces of the cell gate patterns. The active patterns share the cell gate patterns in the stacked-gate structures.

Abstract: One-dimensional acceleration sensor includes: a semiconductor substrate having a constant thickness; parallel second through trenches through the substrate defining a flexible beam therebetween, having width significantly smaller than thickness; four piezo resistors formed at four corner regions of the flexible beam; first through trench through the substrate, continuous with ends of the first through trenches to define a weight continuous with one end of the flexible beam, including a pair of symmetrical first portions sandwiching the flexible beam and a second portion coupling the first portions and one end of the flexible beam, and having a center of gravity at an intermediate position on a longitudinal center line of the flexible beam; and one-layer wirings formed above the flexible beam, serially connecting piezo resistors at a same edge, and leading interconnection points generally along a longitudinal direction of the flexible beam.

Abstract: A semiconductor structure. The semiconductor structure includes: a semiconductor substrate which includes a top substrate surface which defines a reference direction perpendicular to the top substrate surface and further includes a first semiconductor body region and a second semiconductor body region; a first gate dielectric region and a second gate dielectric region on top of the first and second semiconductor body regions, respectively; a first gate electrode region on top of the semiconductor substrate and the first gate dielectric region; a second gate electrode region on top of the semiconductor substrate and the second gate dielectric region; and a gate divider region in direct physical contact with the first and second gate electrode regions. The gate divider region does not overlap the first and second gate electrode regions in the reference direction.

Abstract: A semiconductor device according to the present invention includes: a body region of a first conductive type; trenches formed by digging in from a top surface of the body region; gate electrodes embedded in the trenches; source regions of a second conductive type formed at sides of the trenches in a top layer portion of the body region; and body contact regions of the first conductive type, penetrating through the source regions in a thickness direction and contacting the body region. The body contact regions are formed in a zigzag alignment in a plan view.

Abstract: There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein a bulk semiconductor material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and an insulation material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages of body-tied structures.

Abstract: There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein an insulation material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and a bulk semiconductor material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages such as low cost and high heat transfer.

Abstract: A memory array includes a plurality of bit lines and a plurality of word lines, a gate region, and a charge trapping layer. The charge trapping layer is wider than a word line; the charge trapping layer is extended beyond the edge of the gate region to facilitate capturing and removing charges.

Abstract: A low resistance electrode and a compound semiconductor light emitting device including the same are provided. The low resistance electrode deposited on a p-type semiconductor layer of a compound semiconductor light emitting device including an n-type semiconductor layer, an active layer, and the p-type semiconductor layer, including: a reflective electrode which is disposed on the p-type semiconductor layer and reflects light being emitted from the active layer; and an agglomeration preventing electrode which is disposed on the reflective electrode layer in order to prevent an agglomeration of the reflective electrode layer during an annealing process.

Abstract: Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. An embodiment may include forming hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as atomic layer deposition.

Abstract: Provided are a light emitting device package and a lighting system. The light emitting device package includes a light emitting device chip, at least one wire, and an encapsulating material. The light emitting device chip includes a first conductive type semiconductor layer, a second conductive type semiconductor layer on the first conductive type semiconductor layer, and an active layer between the first and second conductive type semiconductor layers. The wire is on the light emitting device chip. The encapsulating material is on the light emitting device chip out of the wire, and includes a phosphor. The wire is perpendicular to an upper surface of the light emitting device chip, at least up to a height of the encapsulating material.

Abstract: Provided are a light emitting device package and a lighting system comprising the same. The light emitting device package comprises a package body having a trench, a metal layer within the trench, and a light emitting device over the metal layer.

Abstract: An optoelectronic component is specified that emits a useful radiation. It comprises a housing having a housing base body with a housing cavity, and a light-emitting diode chip arranged in the housing cavity. At least one base body material of the housing base body has radiation-absorbing particles admixed in a targeted manner to reduce its reflectivity. According to another embodiment of the component, the housing additionally or alternatively has a housing material transmissive for the useful radiation that has radiation-absorbing particles admixed in a targeted manner to reduce its reflectivity. In addition, a method for manufacturing such a component is specified.