Abstract: An integrated circuit structure includes a semiconductor substrate; a conductive via (TSV) passing through the semiconductor substrate; and a copper-containing post overlying the semiconductor substrate and electrically connected to the conductive via.

Abstract: After a plurality of pads (2) are formed on an insulation film (1), a passivation film (3) is formed on the entire surface thereof, and opening parts (3a) which exposes all the pads (2) are formed in the passivation film (3). Next, another passivation film is formed on the entire surface and, for each of the pads (2), an opening part is formed in this passivation film to expose the central portion of the pad (2). According to the above method, the probing test can be performed with the opening parts (3a) formed in the passivation film (3). Performing the probing test in such a state increases the probability that the probe contacts the pad (2) since the entire surface of the pad (2) is exposed, thereby providing the test with a higher accuracy. Thus, the pad can be miniaturized and/or the pitch can be narrowed without requiring a higher accuracy of the probe.

Abstract: A semiconductor memory device includes: a lower pillar protruding from a substrate in a vertical direction and extending in a first direction by a trench formed in the first direction; an upper pillar protruding on the lower pillar in a second direction perpendicular to the first direction; a buried bit line junction region disposed on one sidewall of the lower pillar; a buried bit line contacting the buried bit line junction region and filling a portion of the trench; an etch stop film disposed on an exposed surface of the buried bit line; a first interlayer dielectric film recessed to expose a portion of an outer side of at least the upper pillar disposed on the etch stop film; a second interlayer dielectric film disposed on the first interlayer dielectric film; and a gate surrounding the exposed outer side of the upper pillar and crossing the buried bit line.

Abstract: An integrated circuit structure can include a first interposer and a second interposer. The first interposer and the second interposer can be coplanar. The integrated circuit structure further can include at least a first die that is coupled to the first interposer and the second interposer.

Abstract: Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging microfeature devices in accordance with an embodiment of the invention can include releasably attaching a plurality of first known good microelectronic dies to a carrier substrate in a desired arrangement. In several embodiments, for example, the first dies can be releasably attached to an attachment feature on the carrier substrate. The method can also include attaching one or more second known good microelectronic dies to the individual first dies in a stacked configuration to form a plurality of stacked devices. The method further includes at least partially encapsulating the stacked devices and separating the stacked devices from each other.

Abstract: A light emitting diode chip a support layer having a first face and a second face opposite the first face, a diode region on the first face of the support layer, and a bond pad on the second face of the support layer. The bond pad includes a gold-tin structure having a weight percentage of tin of 50% or more. The light emitting diode chip may include a plurality of active regions that are connected in electrical series on the light emitting diode chip.

Abstract: A semiconductor light emitting device has a multilayer epitaxial structure for emitting light by a light emitting layer located between a first conductive layer and a second conductive layer. The multilayer epitaxial structure can be grown directly on a base substrate. A reflective layer can be provided in the multilayer epitaxial structure between the base substrate and the first conductive layer. A distributive Bragg reflector can be positioned adjacent the substrate. A surface of the multilayer epitaxial structure can be conformed to provide improved light extraction. A phosphorus film encapsulates the multilayer epitaxial structure and its respective side surfaces.

Abstract: Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in a transistor. An embodiment may include forming a hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as reaction sequence atomic layer deposition.

Abstract: It is an object to provide a memory device where an area occupied by a memory cell is small, and moreover, a memory device where an area occupied by a memory cell is small and a data holding period is long. A memory device includes a bit line, a capacitor, a first insulating layer provided over the bit line and including a groove portion, a semiconductor layer, a second insulating layer in contact with the semiconductor layer, and a word line in contact with the second insulating layer. Part of the semiconductor layer is electrically connected to the bit line in a bottom portion of the groove portion, and another part of the semiconductor layer is electrically connected to one electrode of the capacitor in a top surface of the first insulating layer.

Abstract: A light emitting device is provided with a base member, an interconnect pattern disposed on an upper surface of the base member, a light reflecting layer comprising a first layer disposed on a part of the interconnect pattern and formed from a metal material, and a second layer made of a dielectric multilayer reflecting film made with stacked layers of dielectric films having different refractive indices and covering an upper surface and side surfaces of the first layer, a light emitting element chip fixed so as to face at least a part of the light reflecting layer, and a light transmissive sealing member sealing the light reflecting layer and the light emitting element chip.

Abstract: Provided are a semiconductor device which enables reduction of diffusion of Si in the manufacturing process of an MIPS element and suppression of an increase in EOT, and a method of manufacturing the same. An embodiment of the present invention is a semiconductor device including a field effect transistor having a gate insulating film provided on a silicon substrate and a gate electrode provided on the gate insulating film. The gate electrode is a stack-type electrode including a conductive layer containing at least Ti, N, and O (oxygen) and a silicon layer provided on the conductive layer, and the concentration of oxygen in the conductive layer is highest in the side of the silicon layer.

Abstract: An integrated circuit die includes a substrate having an upper surface, at least one active device formed in a first area of the upper surface of the substrate, and a plurality of layers formed on the upper surface of the substrate above the at least one active device. A first stacked heat conducting structure is provided, spanning from a point proximate the first area of the upper surface of the substrate through the plurality of layers. A lateral heat conducting structure is formed above the uppermost layer of the plurality of layers and in thermal contact with the first stacked heat conducting structure. The invention advantageously facilitates the dissipation of heat from the integrated circuit die, particularly from high-power sources or other localized hot spots.

Abstract: The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel, with two control gates, a front control gate located above the floating gate and separated from it by an inter-gate dielectric, and a back control gate located within the base substrate directly under the insulating (BOX) layer and separated from the channel by only the insulating (BOX) layer. The two control gates are designed to be used in combination to perform a cell programming operation. The invention also relates to a memory array made up of a plurality of memory cells according to the first aspect of the invention, which can be in an array of rows and columns, and a method of fabricating such memory cells and memory arrays.

Abstract: Provided are a phosphor, a phosphor manufacturing method, and a white light emitting device. The phosphor is represented as a chemical formula of aMO-bAlN-cSi3N4, which uses light having a peak wavelength in a wavelength band of about 350 nm to about 480 nm as an excitation source to emit visible light having a peak wavelength in a wavelength band of about 480 nm to about 680 nm. (where M is one selected from alkaline earth metals (0.2?a/(a+b)?0.9, 0.05?b(b+c)?0.85, 0.4?c/(c+a)?0.9)).

Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

Abstract: A method for producing a SiGe stressor with high Ge concentration is provided. The method includes providing a semiconductor substrate with a source area, a drain area, and a channel in between; depositing the first SiGe film layer on the source area and/or the drain area; performing a low temperature thermal oxidation, e.g., a high water vapor pressure wet oxidation, to form an oxide layer at the top of the first SiGe layer and to form the second SiGe film layer with high Ge percentage at the bottom of the first SiGe film layer without Ge diffusion into the semiconductor substrate; performing a thermal diffusion to form the SiGe stressor from the second SiGe film layer, wherein the SiGe stressor provides uniaxial compressive strain on the channel; and removing the oxide layer. A Si cap layer can be deposited on the first SiGe film layer prior to performing oxidation.

Abstract: A semiconductor package including a substrate, a semiconductor device, a protection layer, a bonding wire, and a molding compound is provided. The substrate has a contact pad and a solder mask, and the contact pad is exposed from the solder mask. The semiconductor device is disposed on the substrate. The protection layer is disposed on the contact pad. The bonding wire connects the semiconductor device to the contact pad. An end of the bonding wire penetrates the protection layer and bonds with a portion of a surface of the contact pad to form a bonding region. The protection layer covers an entire surface of the contact pad except the bonding region. The molding compound covers the semiconductor device, the contact pad, and the bonding wire.

Abstract: It is an object of the present invention to provide a nonvolatile memory device, in which additional writing is possible other than in manufacturing and forgery and the like due to rewriting can be prevented, and a semiconductor device having the memory device. It is another object of the present invention to provide an inexpensive and nonvolatile memory device with high reliability and a semiconductor device. According to one feature of the present invention, a memory device includes a first conductive layer formed over an insulating surface, a second conductive layer, a first insulating layer interposed between the first conductive layer and the second conductive layer, and a second insulating layer which covers a part of the first conductive layer, wherein the first insulating layer covers an edge portion of the first conductive layer, the insulating surface, and the second insulating layer.

Abstract: A mounting substrate for a semiconductor light emitting device includes a solid metal block having first and second opposing metal faces. The first metal face includes an insulating layer and a conductive layer on the insulating layer. The conductive layer is patterned to provide first and second conductive traces that connect to a semiconductor light emitting device. The second metal face may include heat sink fins therein. A flexible film including an optical element, such as a lens, also may be provided, overlying the semiconductor light emitting device.

Abstract: The invention notably concerns a method for depositing nano-objects on a surface. The method includes: providing a substrate with surface patterns on one face thereof; providing a transfer layer on said face of the substrate; functionalizing areas on a surface of the transfer layer parallel to said face of the substrate, at locations defined with respect to said surface patterns, such as to exhibit enhanced binding interactions with nano-objects; depositing nano-objects and letting them get captured at the functionalized areas; and thinning down the transfer layer by energetic stimulation to decompose the polymer into evaporating units, until the nano-objects reach the surface of the substrate. The invention also provides a semiconductor device which includes a substrate and nano-objects accurately disposed on the substrate.