Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

Abstract: One embodiment of the present invention sets forth an integrated circuit package including a substrate, an integrated circuit die, and a plurality of solder bump structures. The substrate includes a first plurality of interconnects disposed on a first surface of the substrate. The integrated circuit die includes a second plurality of interconnects disposed on a first surface of the integrated circuit die. The plurality of solder bump structures couple the first plurality of interconnects to the second plurality of interconnects. The first plurality of interconnects are configured to be substantially aligned with the second plurality of interconnects when the integrated circuit package is at a first temperature within a range of about 0° C. to about ?100° C. The first plurality of interconnects are configured to be offset from the second plurality of interconnects when the integrated circuit package is at a temperature above the first temperature.

Abstract: An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line.

Abstract: A light emitting diode structure includes a diode region and a metal stack on the diode region. The metal stack includes a barrier layer on the diode region and a bonding layer on the barrier layer. The barrier layer is between the bonding layer and the diode region. The bonding layer includes gold, tin and nickel. A weight percentage of tin in the bonding layer is greater than 20 percent and a weight percentage of gold in the bonding layer is less than about 75 percent. A weight percentage of nickel in the bonding layer may be greater than 10 percent.

Abstract: Provided is a semiconductor device. A semiconductor chip is disposed on a substrate. A first magnetic substance, a second magnetic substance and a third magnetic substance which are spaced apart from one another are formed on the semiconductor chip. The first magnetic substance and the second magnetic substance can be adjacent an edge of the semiconductor chip. The third magnetic substance can be adjacent a center of the semiconductor chip. The third magnetic substance is between the first magnetic substance and the second magnetic substance.

Abstract: A method for providing and operating a device in a first mode as a light-emitting transistor and in a second mode as a high speed electrical transistor, including the following steps: providing a semiconductor base region of a first conductivity type between semiconductor emitter and collector regions of a second semiconductor type; providing, in the base region, a quantum size region; providing, in the base region between the quantum size region and the collector region, a carrier transition region; applying a controllable bias voltage with respect to the base and collector regions to control depletion of carriers in at least the carrier transition region; and applying signals with respect to the emitter, base, and collector regions to operate the device as either a light-emitting transistor or a high speed electrical transistor, depending on the controlled bias signal.

Abstract: In one embodiment, a semiconductor package includes a first semiconductor die having a first surface facing upwardly to expose a bond pad, a second semiconductor die having a first surface facing downwardly to expose a bond pad and disposed to be offset with the first surface of the first semiconductor die, and an encapsulant encapsulating the first semiconductor die and the second semiconductor die together. Throughholes are disposed in the encapsulant adjacent the bond pad of the first semiconductor die and adjacent the bond pad of the second semiconductor die.

Abstract: A system that incorporates teachings of the subject disclosure may include, for example, a method for depositing a first material that substantially covers a nanoheater, applying a signal to the nanoheater to remove a first portion of the first material covering the nanoheater to form a trench aligned with the nanoheater, depositing a second material in the trench, and removing a second portion of the first material and a portion of the second material to form a nanowire comprising a remaining portion of the second material covering the nanoheater along the trench. Additional embodiments are disclosed.

Abstract: A Schottky barrier diode includes an n-type semiconductor layer including a Ga2O3-based compound semiconductor with n-type conductivity, and an electrode layer that is in Schottky-contact with the n-type semiconductor layer. A first semiconductor layer in Schottky-contact with the electrode layer and a second semiconductor layer having an electron carrier concentration higher than the first semiconductor layer are formed in the n-type semiconductor layer. The second semiconductor layer includes a ?-Ga2O3 substrate including a main plane rotated by an angle not less than 50° and not more than 90° with respect to a (100) plane thereof.

Abstract: An inverter is implemented in an FDSOI integrated circuit die. The inverter includes a PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors each include a first gate coupled to the respective source terminal of the transistor. The PMOS and NMOS transistors each include a back gate coupled to the input of the inverter.

Abstract: First, second, and third power wirings and plurality of first signal wirings are formed on the upper layer of a semiconductor substrate, and at least one second signal wiring is formed on the upper layer of the plurality of first signal wirings. First and second power wirings are mutually separated in the cell height direction and extended in the cell width direction. Third power wiring extends between the first and second power wirings in the cell width direction. The plurality of first signal wirings are separated from first, second, and third power wirings, and electrically connected to at least one of the plurality of circuit elements. At least one second signal wiring extends in the cell width direction, and electrically connected to at least one of the plurality of circuit elements and the plurality of first signal wirings.

Abstract: The disclosure relates to a light emitting diode. The light emitting diode includes a first semiconductor layer, an active layer, and a second semiconductor layer, a first electrode, a second electrode and a nanotube film. The first semiconductor layer, the active layer, and the second semiconductor layer are stacked with each other in that order. The first electrode is electrically connected with the second semiconductor layer. The second electrode is electrically connected with the first semiconductor layer. The nanotube film is located on one of the first semiconductor layer, the active layer and the second semiconductor layer. The nanotube film comprises a number of nanotubes orderly arranged and combined with each other by ionic bonds.

Abstract: A package on package structure providing mechanical strength and warpage control includes a first package component, a second package component, and a first set of conductive elements coupling the first package component to the second package component. A first polymer-comprising material is molded on the first package component and surrounds the first set of conductive elements. The first polymer-comprising material has an opening therein exposing a top surface of the second package component. A third package component and a second set of conductive elements couples the second package component to the third package component.

Abstract: A jointed structure comprises a first metal layer and a second metal layer. The first metal layer and the second metal layer are jointed together and have different coefficients of thermal expansion. The first metal layer and the second metal layer are jointed together by solid-phase joining via a jointing interface microstructure, wherein the jointing interface microstructure includes an amorphous oxide phase and having a thickness of 50 nm or less.

Abstract: An electrically conducting, vertically displacing microelectromechanical system (MEMS) is formed on a first integrated circuit chip. The first integrated circuit chip is physically connected to a three-dimensional packaging structure. The three-dimensional packaging structure maintains a fixed distance between the first integrated circuit chip and a second integrated circuit chip. A control circuit is operatively connected to the MEMS. The control circuit directs movement of the MEMS between a first position and a second position. The MEMS makes contact with a contact pad on the second integrated circuit chip when it is in the second position forming a conductive path and providing electrical communication between the first integrated circuit chip and the second integrated circuit chip. The MEMS avoids making contact with the contact pad on the second integrated circuit chip when it is in the first position.

Abstract: A semiconductor package component (3) is mounted on a substrate (1) in such a manner that an electrode (2) of the substrate (1) and an electrode of the semiconductor package component (3) are brought into contact with each other through a joining material (4). A reinforcing adhesive (5c) is applied between the substrate (1) and the outer surface of the semiconductor package component (3). Then, reflow is performed to melt the joining metal (4) with the reinforcing adhesive (5c) uncured. After the reinforcing adhesive (5c) is cured, the joining metal (4) is solidified.

Abstract: A semiconductor device is provided with: a semiconductor substrate; an insulation film formed above the semiconductor substrate; a pad formed on the insulation film, the pad including a trace; a first passivation film formed on the insulation film, located adjacent the pad, and separated from the pad; and a second passivation film formed on the first passivation film and the pad, the second passivation film covering the trace, and the second passivation film including an opening which exposes a part of the pad.

Abstract: For simplification of a structure and a manufacturing process of an element, and reduction of manufacturing cost, the present disclosure provides a light-receiving device including: a photoelectric conversion element; and an active element, wherein the active element includes at least one of a reset element configured to reset the photoelectric conversion element, an amplifier element configured to amplify a detection signal based on the photoelectric conversion element, or a selection element configured to selectively output the detection signal based on the photoelectric conversion element, and the photoelectric conversion element and at least part of the active element are formed by using an identical organic semiconductor material or an identical high molecular functional material.

Abstract: In one general aspect, an apparatus can include an anode terminal, and a cathode terminal. The apparatus can include a junction field-effect transistor (JFET) portion having a channel disposed within a semiconductor substrate and defining a first portion of an electrical path between the anode terminal and the cathode terminal. The apparatus can also include a diode portion formed within the semiconductor substrate and defining a second portion of the electrical path between the anode terminal and the cathode terminal. The diode portion can be serially coupled to the channel of the JFET device.

Abstract: A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.