Patents Examined by Hong Kim
  • Patent number: 10095629
    Abstract: Generally discussed herein are systems, devices, and methods for local and remote dual address decoding. According to an example a node can include one or more processors to generate a first memory request, the first memory request including a first address and a node identification, a caching agent coupled to the one or more processors, the caching agent to determine that the first address is homed to a remote node remote to the local node, a network interface controller (NIC) coupled to the caching agent, the NIC to produce a second memory request based on the first memory request, and the one or more processors further to receive a response to the second memory request, the response generated by a switch coupled to the NIC, the switch includes a remote system address decoder to determine a node identification to which the second memory request is homed.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Francesc Cesc Guim Bernat, Kshitij A. Doshi, Steen Larsen, Mark A Schmisseur, Raj K. Ramanujan
  • Patent number: 10073647
    Abstract: Methods, systems, and apparatuses are described for provisioning storage devices. An example method includes specifying a logical zone granularity for logical space associated with a disk drive. The method further includes provisioning a zone of a physical space of the disk drive based at least in part on the specified logical zone granularity. The method also includes storing compressed data in the zone in accordance with the provisioning.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: September 11, 2018
    Inventor: Timothy R. Feldman
  • Patent number: 10067679
    Abstract: Embodiments relate to avoiding out-of-space conditions in storage controllers operating with efficiency capabilities between virtual space in a data container and real space in a storage container. Both the real space and the virtual space are monitored. The real space usage is compared to a threshold to provide information about occupancy of the real space. A virtual size of the virtual object is adjusted responsive to the real space usage meeting or exceeding the threshold.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bulent Abali, David D. Chambliss, Joseph S. Glider, Luis A. Lastras-Montano, Cameron J. McAllister
  • Patent number: 10048868
    Abstract: Systems, apparatuses and methods may provide for identifying a first block and a second block, wherein the first block includes a first plurality of cache lines, the second block includes a second plurality of cache lines, and the second block resides in a memory-side cache. Additionally, each cache line in the first plurality of cache lines may be compressed with a corresponding cache line in the second plurality of cache lines to obtain a compressed block that includes a third plurality of cache lines. In one example, the second block is replaced in the memory-side cache with the compressed block if the compressed block satisfies a size condition.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Alaa R. Alameldeen, Glenn J. Hinton, Blaise Fanning, James J. Greensky
  • Patent number: 10049053
    Abstract: An external storage resource pool associated with federated tiered storage is associated with at least one performance tier based on evaluated performance of the external storage resource pool. Performance of the external pool may be evaluated in terms of service level expectations or service level objectives. Workload pattern analysis or performance probability curves may be used to classify the external storage resource pool. Workload distribution may be determined by a margin analysis algorithm that matches workloads and storage resource pool performance characteristics.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: August 14, 2018
    Inventors: Malak Alshawabkeh, Owen Martin, Xiaomei Liu, Sean Dolan, Hui Wang
  • Patent number: 10042750
    Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a processing unit configured to run an operating system, and a memory coupled to the processing unit. The memory configured to communicate with the processing unit via a memory bus. The example apparatus may further include an adaptive memory controller configured to receive monitored statistical data from the memory and from the processing unit. The adaptive memory controller is configured to manage the memory based on the monitored statistical data.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: August 7, 2018
    Assignee: Micron Technology, Inc.
    Inventors: David A. Roberts, J. Thomas Pawlowski, Robert Walker
  • Patent number: 10021148
    Abstract: In one embodiment, a computer-implemented method includes: receiving a request to establish a Peer-to-Peer Remote Copy (PPRC) relationship between a primary storage system and a secondary storage system; and copying one or more data tracks of a primary storage device in the primary storage system to the secondary storage system without copying at least one other data track of the primary storage device to the secondary storage system. The one or more data tracks of the primary storage device comprise one or more data tracks of a first characteristic. Other portions of the primary storage device comprise one or more other data tracks of a second characteristic. Tracks of the first characteristic may include valid data records, while tracks of the second characteristic may include invalid data records and/or empty tracks. Corresponding systems and computer program products are also disclosed.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: July 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Gavin S. Johnson, Michael J. Koester, Kevin L. Miner
  • Patent number: 9996295
    Abstract: A semiconductor memory device and a scrambling method thereof are provided, which are capable of realizing a balance between a data scrambling function and an accessible time. The semiconductor memory device of the invention includes a page buffer/sense circuit with the data scrambling function. During a programming operation, the page buffer/sense circuit holds data to be programmed, performs a scrambling process on the held data and programs the scrambled data to a selected page of a memory array. During a reading operation, the page buffer/sense circuit holds data read from the selected page and performs a descrambling process on the held data.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: June 12, 2018
    Assignee: Winbond Electronics Corp.
    Inventor: Naoaki Sudo
  • Patent number: 9977611
    Abstract: According to one embodiment, a storage device includes a storage, first data in which a sequence number indicating a write-completion order is associated with each erase unit area included in areas of the storage, second data indicating a relationship between each write interval and each write destination, a selection module which obtains the erase unit area corresponding to a logical address of target data to be written, calculates a write interval of the target data from a difference between the sequence number at an occurrence time of writing and the sequence number corresponding to the erase unit area of the first data, and selects the write destination corresponding to the write interval of the target data, and a write module which writes the target data to the selected write destination, and changes the sequence number when writing is completed for one erase unit area.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: May 22, 2018
    Inventor: Kazunori Sekido
  • Patent number: 9971700
    Abstract: A processing device includes a cache implementing a set of at least three cache slices. Each cache slice is to store a corresponding set of cache lines. The cache further includes cache control logic coupled to the set of at least three cache slices. The cache control logic is to map addresses of an address space to the cache such that each address within the address space maps to a corresponding strict subset of two or more cache slices of the set of cache slices.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: May 15, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Gabriel H. Loh
  • Patent number: 9952982
    Abstract: Provided are a computer program product, system, and method for invoking demote threads on processors to demote tracks from a cache. A plurality of demote ready lists indicate tracks eligible to demote from the cache. In response to determining that a number of free cache segments in the cache is below a free cache segment threshold, a determination is made of a number of demote threads to invoke on processors based on the number of free cache segments and the free cache segment threshold. The determined number of demote threads are invoked to demote tracks in the cache indicated in the demote ready lists, wherein each invoked demote thread processes one of the demote ready lists to select tracks to demote from the cache to free cache segments in the cache.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: April 24, 2018
    Inventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Trung N. Nguyen
  • Patent number: 9952805
    Abstract: A processor receives a command from a server computer to designate a plurality of addresses related to a plurality of logical storage areas, and write a plurality of write data to the logical storage areas. The processor receives the write data and writes it to storage areas different from storage areas in which a plurality of holding data are stored in a first memory. When the processor determines that the write data are written to the first memory, the processor transmits a success response to a host computer. When the write data satisfy a predetermined condition, the processor writes the write data in the first memory to a plurality of first device storage areas. When it is determined that at least a part of the data is not written to the first memory, the processor transmits a failure response to the host computer.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: April 24, 2018
    Assignee: HITACHI, LTD.
    Inventors: Takashi Nagao, Tomohiro Kawaguchi, Yoshinori Oohira
  • Patent number: 9952769
    Abstract: Operations of a variety of components of a storage system stack are redefined to make the system more efficient when the underlying media has a “multi-log” type interface such as the case with NAND flash SSD memory or shingled magnetic recording media. The responsibilities of components of the storage system stack are modified such that each responsibility is performed at the most efficient component (level of abstraction) of the storage stack.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: April 24, 2018
    Inventors: Anirudh Badam, Bikash Sharma, Laura Marie Caulfield, Badriddine Khessib, Suman Kumar Nath, Jian Huang
  • Patent number: 9952793
    Abstract: A memory system may include: a memory device including a plurality of pages having a plurality of memory cells coupled to a plurality of word lines and suitable for storing read data and write data requested from a host, a plurality of memory blocks each including the pages, a plurality of planes each including the memory blocks, and a plurality of memory chips each including the planes; and a controller suitable for searching map data of the read data corresponding to a read command received from the host on a basis of a plurality of segments, triggering memory chips corresponding to the map data searched through the searches of the respective segments, reading data stored in the triggered memory chips, and transferring the read data to the host.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: April 24, 2018
    Assignee: SK Hynix Inc.
    Inventor: Jeen Park
  • Patent number: 9940231
    Abstract: An approach for erasing data being stored in a data storage apparatus is provided, which may be provided e.g. as an apparatus, as a method, as a system or as a computer program. A sequence of uncompressible data is obtained fulfilling predetermined criteria, which includes a statistical measure indicative of compressibility or uncompressibility of the sequence of uncompressible data meeting a predetermined criterion, wherein the sequence of uncompressible data is divided into one or more blocks of uncompressible data, the sum of the sizes of the one or more blocks of uncompressible data being larger than or equal to the storage capacity of the data storage apparatus. The one or more blocks of uncompressible data is provided to the data storage apparatus for storage therein to overwrite the data currently stored in the data storage apparatus.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: April 10, 2018
    Assignee: Blancco Oy Ltd
    Inventors: Kim Vaisanen, Lauri Lalli, Jonathan Brew
  • Patent number: 9933948
    Abstract: According to one embodiment, a tiered storage system includes a tiered storage device and a computer. The computer uses the tiered storage device, and includes a file system and a correction support unit. If an access request from an application is a write request to request overwriting of data, the file system executes a copy-on-write operation. The correction support unit causes the storage controller to carry over an access count manacled by the storage controller and associated with the logical block address of a copy source in the copy-on-write operation, to an access count associated with the logical block address of a copy destination in the copy-on-write operation.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: April 3, 2018
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Solutions Corporation
    Inventors: Shouhei Saitou, Shinya Ando
  • Patent number: 9916116
    Abstract: Dynamically replicated memory is usable to allocate new memory space from failed memory pages by pairing compatible failed memory pages to reuse otherwise unusable failed memory pages. Dynamically replicating memory involves detecting and recording memory faults, reclaiming failed memory pages for later use, recovering from detected memory faults, and scheduling access to replicated memory pages.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: March 13, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Engin Ipek, Douglas Christopher Burger, Thomas Moscibroda, Edmund Bernard Nightingale, Jeremy P. Condit
  • Patent number: 9898747
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a first controller which controls the nonvolatile memory, a wireless antenna, a memory, a second controller, and a third controller. The wireless antenna generates electric power based on a radio wave from a first external device. The memory is operable based on the generated electric power. The second controller is operable based on the generated electric power and controls communication using the wireless antenna. The third controller controls data copy or transfer between the nonvolatile memory and the memory. The third controller receives, from a second external device, identification information and stores the identification information in the memory. The second controller transmits login information and identification information stored in the memory to the first external device via the wireless antenna.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: February 20, 2018
    Inventors: Keisuke Sato, Masaomi Teranishi, Shuichi Sakurai, Masahiko Nakashima, Shigeki Koizumi, Michio Ido, Shigeto Endo
  • Patent number: 9892035
    Abstract: A memory system supporting an interleaving operation including: a plurality of memory devices; and a controller suitable for detecting whether, among a plurality of logical address groups inputted to perform a read or write operation in the plurality of memory devices, first logical address groups having values related to each other are inputted, and for adjusting, when physical storage locations of data corresponding to logical addresses of the first logical address groups are inaccessible using interleaving, the physical storage locations of the data to locations that are accessible using interleaving and store the data in adjusted locations.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: February 13, 2018
    Assignee: SK Hynix Inc.
    Inventor: Hae-Gi Choi
  • Patent number: 9886384
    Abstract: The present examples relate to prefetching, and to a cache control device for prefetching and a prefetching method using the cache control device, wherein the cache control device analyzes a memory access pattern of program code, inserts, into the program code, a prefetching command generated by encoding the analyzed access pattern, and executes the prefetching command inserted into the program code in order to prefetch data into a cache, thereby maximizing prefetching efficiency.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: February 6, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-Kyoung Kim, Dong-Hoon Yoo, Jeong-Wook Kim, Soo-Jung Ryu