Abstract: The assignment of data storage resources in a data storage arrangement having a plurality of pools, where each pool includes a plurality of data storage resources arranged in tiers, can be optimized. A gap analysis can be performed for each tier of each pool to determine that tier's excess capacity or demand. The effect of switching data storage resources between tiers of different pools can be modeled to determine the effect of the switch on excess capacity and demand. An improved arrangement of data storage resources in the tiers can be determined that reduces excess capacity and demand, from the modeling of the effect of switching data storage resources between pools. At least one data storage resource can be switched from the tier of the first pool to the tier of the second pool to match the determined improved arrangement of data storage resources.

Abstract: A separate distributed buffer cache system may be implemented for a storage client of a distributed storage system. Storage I/O requests may be sent from a storage client to one or more buffer cache nodes in a distributed buffer cache system that maintain portions of an in-memory buffer cache to which the requests pertain. The distributed buffer cache system may send the write requests on to the distributed storage system to be completed, and in response to receiving acknowledgements from the storage system, sending a completion acknowledgement back to the storage client. Buffer cache nodes may update buffer cache entries for received requests such that they are not available for reads until complete at the distributed storage system. For read requests where the buffer cache entries at the buffer cache node are invalid, valid data may be obtained from the distributed storage system and sent to the storage client.

Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.

Abstract: A memory monitoring method and a computing system. The computing system includes a processor, a memory and a monitor. The monitor obtains memory unit access information and process information of the computer system. The memory unit access information includes the number of access times of each memory unit of the memory. The process information includes information about a mapping relationship between a virtual address and a physical address of each memory units accessed by the current running process. After generating monitoring information, which includes the frequency at which the current running process accesses each memory unit, according to the memory unit access information and the process information, the monitor feeds the monitoring information back to the processor. Thus, the processor can perform memory management according to the monitoring information.

Abstract: A processor system (10) includes: a first memory controller (16) that controls writing/reading data to/from a first memory (60); a second memory controller (17) that controls writing/reading data to/from a second memory (70); a first processor (13) that inputs and outputs the data from and to the first memory through a bus (14); a second processor (11) that inputs and outputs processed data from and to the second memory through the bus; and a management unit 32 that deallocates an address range corresponding to the second memory from the first process and allocates the address range to the second processor.

Abstract: In one embodiment, the present disclosure describes a method of optimizing memory access in a hierarchical memory system. The method includes determining a request rate from an ith layer of the hierarchical memory system for each of n layers in the hierarchical memory system. The method also includes determining a supply rate from an (i+1)th layer of the hierarchical memory system for each of the n layers in the hierarchical memory system. The supply rate from the (i+1)th layer of the hierarchical memory system corresponds to the request rate from the ith layer of the hierarchical memory system. The method further includes adjusting a set of computer architecture parameters of the hierarchical memory system or a schedule associated with an instruction set to utilize heterogeneous computing resources within the hierarchical memory system to match a performance of each adjacent layer of the hierarchical memory system.

Abstract: Described are techniques for creating windows of free blocks in a file system selected in accordance with trigger conditions. A first slice is selected, in accordance with slice selection criteria, from a plurality of slices of storage provisioned for use by the file system. First processing is performed on the first slice that creates at least one window of free blocks in the first slice for use by the file system. It is determined, in accordance with termination criteria, whether to process one or more additional slices of the file system to create additional windows of free blocks for use by the file system. Such processing to create free windows may be subject to various limits of resource consumption.

Abstract: Described herein is a system and method for retaining deduplication of data blocks of a resulting storage object (e.g., a flexible volume) from a split operation of a clone of a base storage object. The clone may comprise data blocks that are shared with at least one data block of the base storage object and at least one data block that is not shared with at least one data block of the base storage object. The data blocks of the clone that are shared with the base storage object may be indicated to receive a write allocation that may comprise assigning a new pointer to an indicated data block. Each data block may comprise a plurality of pointers comprising a virtual address pointer and a physical address pointer. As such, data blocks of the clone comprising the same virtual address pointer may be assigned a single physical address pointer. Thus, a new physical address pointer is assigned or allocated once to a given virtual address pointer of data blocks of a clone.

Abstract: The present application is directed to a control circuit that provides a directory configured to maintain a plurality of entries, wherein each entry can indicate sharing of resources, such as cache lines, by a plurality of agents/hosts. Control circuit of the present invention can further provide consolidation of one or more entries having a first format to a single entry having a second format when resources corresponding to the one or more entries are shared by the agents. First format can include an address and a pointer representing one of the agents, and the second format can include a sharing vector indicative of more than one of the agents. In another aspect, the second format can utilize, incorporate, and/or represent multiple entries that may be indicative of one or more resources based on a position in the directory.

Abstract: A hybrid memory controller performs receiving first and second central processing unit (CPU) requests to write to/read from a hybrid memory group, identifying a volatile memory device and a non-volatile memory device as a first target and second target of the first and second CPU requests, respectively, by decoding and address mapping of the first and second CPU requests, queuing the first and second CPU requests in first and second buffers, respectively, generating, based on an arbitration policy, a first command corresponding to one of the first and second CPU requests to an associated one of the first and second targets, and generating a second command corresponding to another one of the first and second CPU requests to an associated another one of the first and second targets, and transmitting the first and second commands to respective ones of the volatile and non-volatile memory devices.

Abstract: A method for performing memory interface calibration in an electronic device, an associated apparatus, and an associated memory controller are provided, where the method includes: controlling a signal on a digital terminal of the memory controller to switch between a plurality of levels, wherein the digital terminal is coupled to a memory of the electronic device; and based on at least one detection result obtained from detecting the signal, calibrating a logical state of the signal to correspond to a level of the plurality of levels. More particularly, the memory controller may include a plurality of command terminals, a plurality of data terminals, and at least one clock terminal, which are used for coupling the memory controller to the memory. For example, the digital terminal may be a command terminal or a data terminal.

Abstract: A storage device communicating with a host includes a plurality of memory devices and a memory controller. Each of the memory devices includes at least one of a plurality of memory areas that have different storage reliability levels. The memory controller controls the memory devices such that data and required level data associated with a required reliability level of the data are stored in some or all of the memory areas. The data and the required level data are provided from the host. The data is stored in a memory area having a storage reliability level corresponding to the required reliability level from among the memory areas, according to a control of the memory controller.

Abstract: A memory device having at least one output predicting a feasibility of whether the memory device will work properly at a different operating condition including a different supply voltage and/or a different operating frequency than the current supply voltage and/or the current operating frequency. A semiconductor device (e.g. a SoC chip) provides a test to either validate or invalidate the feasibility for the memory device to enter such a different operating condition based on read and write operations of the memory device in normal access cycles. The memory device is partitioned with at least a first memory unit and a second memory unit, which can be coupled to different back-bias voltages. This operating condition predicting function can be enabled or disabled by the semiconductor device in real time operation depending on the feasibility test results.

Abstract: A memory system may include: a memory device that operates using a first voltage received from a host and suitable for storing a value of operation information, and waking up from a sleep state in response to a request of the host; and a controller that operates using a second voltage received from the host, and suitable for selectively resetting the memory device according to a result obtained by checking a value of operation information of the memory device, when waking up the memory device in a sleep state according to a request of the host.

Abstract: A method of enabling “fast” suspend and “rapid” resume of virtual machines (VMs) employs a cache that is able to perform input/output operations at a faster rate than a storage device provisioned for the VMs. The cache may be local to a computer system that is hosting the VMs or may be shared cache commonly accessible to VMs hosted by different computer systems. The method includes the steps of saving the state of the VM to a checkpoint file stored in the cache and locking the checkpoint file so that data blocks of the checkpoint file are maintained in the cache and are not evicted, and resuming execution of the VM by reading into memory the data blocks of the checkpoint file stored in the cache.

Abstract: Provided are a computer program product, system, and method for data unit classification in accordance with one embodiment of the present description, in which in response to a data processing command, a storage controller classifies data units of a storage unit as either allocated to a data set or as unallocated to any data set. If allocated to a data set, the storage controller can further classify data set-allocated data units as either containing client data or metadata or as empty. In accordance with one aspect of the present description, the storage controller may bypass data processing of the data units which have not been allocated to any data set or otherwise do not contain client data or metadata. Other aspects of data unit classification in accordance with the present description are described.

Abstract: An application may store data to a dataset comprising a plurality of volumes stored on a plurality of storage systems. The application may request a dataset image of the dataset, the dataset image comprising a volume image of each volume of the dataset. A dataset image manager operates with a plurality of volume image managers in parallel to produce the dataset image, each volume image manager executing on a storage system. The plurality of volume image managers respond by performing requested operations and sending responses to the dataset image manager in parallel. Each volume image manager on a storage system may manage and produce a volume image for each volume of the dataset stored to the storage system. If a volume image for any volume of the dataset fails, or a timeout period expires, a cleanup procedure is performed to delete any successful volume images.

Abstract: Embodiments of the invention relates to avoiding out-of-space conditions in storage controllers operating with efficiency capabilities between virtual space in a data container and real space in a storage container. Both the real space and the virtual space are monitored and their respective usage is compared to provide information about occupancy of the real space to the virtual space. Usage of the containers is balanced by employing a virtual file associated with a reserved portion of free capacity in the virtual space.

Abstract: Techniques for surfacing host-side flash storage capacity to a plurality of VMs running on a host system are provided. In one embodiment, the host system creates, for each VM in the plurality of VMs, a flash storage space allocation in a flash storage device that is locally attached to the host system. The host system then causes the flash storage space allocation to be readable and writable by the VM as a virtual flash memory device.

Abstract: A method includes (a) writing blocks of data to a storage device, pluralities of the blocks of data being organized into macroblocks, macroblocks having a first fixed size, pluralities of the macroblocks being organized into segments, segments having a second fixed size, (b) marking some of the written blocks as deleted, (c) computing a ratio of storage marked as deleted (SMD) from a segment and storage written (SW) to the segment (ratio SMD:SW), and (d) in response to the computed ratio exceeding a threshold value, performing a compaction operation on the segment. Performing the compaction operation on the segment includes (1) copying blocks which have not been marked as deleted from within macroblocks that contain at least one block marked as deleted to a new macroblock of the first fixed size and (2) in response to copying, marking the macroblocks from which the blocks were copied as free for reuse.