Abstract: The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the present disclosure can include an array of memory cells configured to store multiple cache entries per page of memory cells; and sense circuitry configured to determine whether cache data corresponding to a request from a cache controller is located at a location in the array corresponding to the request, and return a response to the cache controller indicating whether cache data is located at the location in the array corresponding to the request.

Abstract: An application may store data to a dataset comprising a plurality of volumes stored on a plurality of storage systems. The application may request a dataset image of the dataset, the dataset image comprising a volume image of each volume of the dataset. A dataset image manager operates with a plurality of volume image managers in parallel to produce the dataset image, each volume image manager executing on a storage system. The plurality of volume image managers respond by performing requested operations and sending responses to the dataset image manager in parallel. Each volume image manager on a storage system may manage and produce a volume image for each volume of the dataset stored to the storage system. If a volume image for any volume of the dataset fails, or a timeout period expires, a cleanup procedure is performed to delete any successful volume images.

Abstract: A memory controller receives a command to perform a memory operation, the command including a data packet comprising a plurality of data divisions. In response to receiving the command, for each individual memory device, the memory controller assigns to the individual memory device a respective data division, the respective data division including a plurality of data segments, and determines a single relative memory address associated with an address specified by the received command. The memory controller assembles a sub-request comprising a single contiguous instruction portion, which includes the single relative memory address and one or more instructions to perform the memory operation, and the respective data division, the respective data division following the single contiguous instruction portion, and transmits the sub-request to every memory portion of the number of memory portions of the individual memory device.

Abstract: A processor is provided with a first memory protection unit applying a first set of permissions and a second memory protection unit applying a second set of permissions. A memory access will only be permitted if both the first set of permissions and the second set of permissions are satisfied. The processor also includes a memory management unit which serves to translate from virtual addresses VA to physical addresses PA. A selectable one of the first memory protection unit and the memory management unit is active at any given time under control of a selection bit set by a hypervisor program executing at an exception level with higher privilege than the exception level at which the guest operating systems execute.

Abstract: Techniques for a data storage cluster and a method for maintaining and updating reliability data and reducing data communication between nodes, are disclosed herein. Each data object is written to a single data zone on a data node within the data storage cluster. Each data object includes one or more data chunks, and the data chunks of a data object are written to a data node in an append-only log format. When parity is determined for a reliability group including the data zone, there is no need to transmit data from other data nodes where the rest of data zones of the reliability group reside. Thus, inter-node data communication for determining reliability data is reduced.

Abstract: For browser cache cleanup, to consider for eviction a data item stored in a cache of a browser application in a device, a probability that the data item will be needed again during a period after the eviction is computed. A type is determined of a network that will be available at the device during the period. A cost is computed of obtaining the data item over a network of the type, from a location of the device during the period. Using the probability and the cost, a weight of the data item is computed. The weight is associated with the data item as a part of associating a set of weights with a set of data items in the cache. The data item is selected for eviction from the cache because the weight is a lowest weight in the set of weights.

Abstract: Methods, apparatus and computer program products implement embodiments of the present invention that include conveying first data from local regions of a local volume of a local storage system to a remote storage system having a remote volume with remote regions in a one-to-one correspondence with the local regions. While conveying the first data, a request is received to update a given local region, and the given local region is marked.

Abstract: In one embodiment, when a secondary application on an electronic device is selected for deactivation, the memory associated with the application can be gathered, compacted and compressed into a memory freezer file. The memory freezer file can be stored in non-volatile memory with a reduced storage footprint compared to a memory stored in a conventional swap file. When the selected application is to be reactivated, the compressed memory in the memory freezer file can be quickly restored to process memory.

Abstract: A method and apparatus for calculating a victim way that is always the least recently used way. More specifically, in an m-set, n-way set associative cache, each way in a cache set comprises a valid bit that indicates that the way contains valid data. The valid bit is set when a way is written and cleared upon being invalidated, e.g., via a snoop address, The cache system comprises a cache LRU circuit which comprises an LRU logic unit associated with each cache set. The LRU logic unit comprises a FIFO of n-depth (in certain embodiments, the depth corresponds to the number of ways in the cache) and m-width. The FIFO performs push, pop and collapse functions. Each entry in the FIFO contains the encoded way number that was last accessed.

Abstract: The disclosed invention enables the operation of an MIMD type, an SIMD type, or coexistence thereof in a multiprocessor system including a plurality of CPUs and reduces power consumption for instruction fetch by CPUs operating in the SIMD type. A plurality of CPUs and a plurality of memories corresponding thereto are provided. When the CPUs fetch instruction codes of different addresses from the corresponding memories, the CPUs operate independently (operation of the MIMD type). On the other hand, when the CPUs issue requests for fetching an instruction code of a same address from the corresponding memories, that is, operate in the SIMD type, the instruction code read from one of the memories by one access is parallelly supplied to the CPUs.

Abstract: A driver enables a first virtual storage director running in a container maintained by a hypervisor to achieve direct memory access to memory of a second virtual storage director running in a different container. An address space is made available to the first virtual storage director. A first portion of the address space is associated with memory allocated to the first virtual storage director by the container. A second portion of the address space is mapped to memory allocated to the second virtual storage director.

Abstract: Provided is an information processing system to improve enjoyment in information processing using data obtained in non-contact communication. The information processing system includes a dedicated figure, a non-contact communication unit, a processing unit, and a first storage unit. The dedicated figure is configured to store data and has a non-contact communication function. The non-contact communication unit is configured to read data from the dedicated figure by using the non-contact communication function of the dedicated figure. The processing unit performs figure data processing based on the data read by the non-contact communication unit. The first storage unit stores the number of times of execution of the figure data processing. Processing details of the figure data processing performed by the processing unit depend on the number of times of execution stored in the first storage unit.

Abstract: A method of operating a controller includes, determining whether an address corresponding to a program operation indicates a lower page or an upper page; waiting for a first waiting time for the program operation to the lower page when the address indicates the lower page; waiting for a second waiting time for the program operation to the upper page when the address indicates the upper page, wherein the second waiting time is longer than the first waiting time; and performing a status read operation on the semiconductor memory device after one of the first waiting time or the second waiting time.

Abstract: A semiconductor device and a method of operating the same are provided. A plurality of memory blocks are erased. It is determined whether a selected memory block among the memory blocks is a lastly erased memory block. The selected memory block or another memory block is programmed according to a result of determination.

Abstract: Command trapping in an input/output virtualization (IOV) host controller (HC) (IOV-HC) of a flash-memory-based storage device is disclosed. In one aspect, an IOV-HC is configured to receive a request from a client register interface (CRI) of one of multiple input/output (I/O) clients. The IOV-HC inspects a content of the request prior to the request being passed to a transport protocol engine. Based on the content, the IOV-HC determines whether the request should be further processed or should be trapped. If the IOV-HC determines that the request should be trapped, the IOV-HC traps the request using a request trap. In some aspects, the IOV-HC generates an interrupt to a virtual machine manager (VMM) to notify the VMM that the request was trapped. In some aspects, the IOV-HC provides a response generation circuit to receive instructions from the VMM to generate a response to the CRI from which the trapped request originated.

Abstract: System, methods and apparatus are described that facilitate access to a memory device. A memory space within the memory device is divided into a plurality of storage bank domains. Thereafter, application interface circuits configured to access the memory space are classified into a plurality of interface groups based on one or more application usage requirements. Each interface group of the plurality of interface groups is assigned to a corresponding storage bank domain from the plurality of storage bank domains. Access between each interface group and the corresponding storage bank domain is then provided, wherein a first application interface circuit of a first interface group accesses a first corresponding storage bank domain while a second application interface circuit of a second interface group accesses a second corresponding storage bank domain.

Abstract: A wear leveling method for a rewritable non-volatile memory module is provided. The method includes: recording a timestamp for each of physical erasing units storing valid data according to a programming sequence of the physical erasing units storing valid data among the physical erasing units, and recording an erase count for each of physical erasing units. The method also includes: selecting a first physical erasing unit from the physical erasing units storing valid data according to the timestamps, selecting a second physical erasing unit from physical erasing units not storing valid data among the physical erasing units according to the erase counts, and writing valid data of the first physical erasing unit into the second physical erasing unit, and marking the first physical erasing unit as a physical erasing unit not storing valid data.

Abstract: Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice.

Abstract: A memory controller receives a command to perform a memory operation, the command including a data packet comprising a plurality of data divisions. In response to receiving the command, for each individual memory device, the memory controller assigns to the individual memory device a respective data division, the respective data division including a plurality of data segments, and determines a single relative memory address associated with an address specified by the received command. The memory controller assembles a sub-request comprising a single contiguous instruction portion, which includes the single relative memory address and one or more instructions to perform the memory operation, and the respective data division, the respective data division following the single contiguous instruction portion, and transmits the sub-request to every memory portion of the number of memory portions of the individual memory device.

Abstract: Method and system for data migration between data generating entities and data storage devices protected by de-clustered RAID algorithm are enhanced by dynamically controlling the I/O activity towards the data storage devices (NVM devices) based on their remaining lifespan (health) with the goal to prevent multiple devices selected for writing a parity stripe information from simultaneous failures. This feature is rendered by polling the remaining health of NVM devices in the RAID pool, computing a weighted lifespan for each NVM device, comparing the latter to an average of all NVM devices in the pool, and adjusting the I/O activity towards the NVM device of interest accordingly. If the weighted lifespan exceeds the average lifespan in the pool, the allowed I/O activity is increased, and if the weighted lifespan is below the average for the pool, then the device in question is sent less “writes”.